The Community for Technology Leaders
International Conference on Hardware/Software Codesign and Systems Synthesis (2004)
Stockholm, Sweden
Sept. 8, 2004 to Sept. 10, 2004
ISBN: 1-58113-937-3
TABLE OF CONTENTS

Additional reviewers (PDF)

pp. xiii-xiv

Future challenges in embedded systems (PDF)

A. Cuomo , Adv. Syst. Technol., STMicroelectronics, USA
pp. 1

Organic computing - on the feasibility of controlled emergence (PDF)

C. Muller-Schloer , Inst. of Syst. Eng. - Syst. & Comput. Archit. (SRA), Hannover Univ., Germany
pp. 2-5

A loop accelerator for low power embedded VLIW processors (PDF)

B. Mathew , Sch. of Comput., Utah Univ., Salt Lake City, UT, USA
A. Davis , Sch. of Comput., Utah Univ., Salt Lake City, UT, USA
pp. 6-11

Dual-pipeline heterogeneous ASIP design (PDF)

S. Radhakrishnan , Sch. of Comput. Sci. & Eng., New South Wales Univ., Sydney, NSW, Australia
Hui Guo , Sch. of Comput. Sci. & Eng., New South Wales Univ., Sydney, NSW, Australia
S. Parameswaran , Sch. of Comput. Sci. & Eng., New South Wales Univ., Sydney, NSW, Australia
pp. 12-17

Fast cycle-accurate simulation and instruction set generation for constraint-based descriptions of programmable architectures (PDF)

S.J. Weber , Electron. Res. Lab., California Univ., Berkeley, CA, USA
M.W. Moskewicz , Electron. Res. Lab., California Univ., Berkeley, CA, USA
M. Gries , Electron. Res. Lab., California Univ., Berkeley, CA, USA
pp. 18-23

Hardware synthesis from coarse-grained dataflow specification for fast HW/SW cosynthesis (PDF)

Hyunuk Jung , Sch. of Electr. Eng. & Comput. Sci., Seoul Nat. Univ., South Korea
Soonhoi Ha , Sch. of Electr. Eng. & Comput. Sci., Seoul Nat. Univ., South Korea
pp. 24-29

Efficient mapping of hierarchical trees on coarse-grain reconfigurable architectures (PDF)

F. Rivera , Departamento de Arquitectura de Computadores y Automatica, Univ. Complutense, Madrid, Spain
M. Sanchez-Elez , Departamento de Arquitectura de Computadores y Automatica, Univ. Complutense, Madrid, Spain
M. Fernandez , Departamento de Arquitectura de Computadores y Automatica, Univ. Complutense, Madrid, Spain
R. Hermida , Departamento de Arquitectura de Computadores y Automatica, Univ. Complutense, Madrid, Spain
pp. 30-35

Detecting overflow detection (PDF)

V. Kotlyar , Sandridge Technol., Inc., White Plains, NY, USA
M. Moudgill , Sandridge Technol., Inc., White Plains, NY, USA
pp. 36-41

Memory accesses management during high level synthesis (PDF)

G. Corre , LESTER, South Brittany Univ., Lorient, France
E. Senn , LESTER, South Brittany Univ., Lorient, France
P. Bornel , LESTER, South Brittany Univ., Lorient, France
N. Julien , LESTER, South Brittany Univ., Lorient, France
E. Martin , LESTER, South Brittany Univ., Lorient, France
pp. 42-47

Parallel programming models for a multi-processor SoC platform applied to high-speed traffic management (PDF)

P.G. Paulin , Central R&D, STMicroelectron., Ottawa, Ont., Canada
C. Pilkington , Central R&D, STMicroelectron., Ottawa, Ont., Canada
M. Langevin , Central R&D, STMicroelectron., Ottawa, Ont., Canada
E. Bensoudane , Central R&D, STMicroelectron., Ottawa, Ont., Canada
pp. 48-53

Benchmark-based design strategies for single chip heterogeneous multiprocessors (PDF)

J.M. Paul , Electr. & Comput. Eng. Dept., Carnegie Mellon Univ., Pittsburgh, PA, USA
D.E. Thomas , Electr. & Comput. Eng. Dept., Carnegie Mellon Univ., Pittsburgh, PA, USA
A. Bobrek , Electr. & Comput. Eng. Dept., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 54-59

Automatic synthesis of system on chip multiprocessor architectures for process networks (PDF)

B.K. Dwivedi , Dept. of Comput. Sci. & Eng., Indian Inst. of Technol. Delhi, New Delhi, India
A. Kumar , Dept. of Comput. Sci. & Eng., Indian Inst. of Technol. Delhi, New Delhi, India
M. Balakrishnan , Dept. of Comput. Sci. & Eng., Indian Inst. of Technol. Delhi, New Delhi, India
pp. 60-65

Modeling operation and microarchitecture concurrency for communication architectures with application to retargetable simulation (PDF)

Xinping Zhu , Dept. of Electr. Eng., Princeton Univ., NJ, USA
Wei Qin , Dept. of Electr. Eng., Princeton Univ., NJ, USA
S. Malik , Dept. of Electr. Eng., Princeton Univ., NJ, USA
pp. 66-71

Cellular handset technology system requirements and integration trends (PDF)

S. Mattisson , Ericsson Mobile Platforms AB, Lund, Sweden
pp. 74

Transaction level modeling: flows and use models (PDF)

A. Donlin , Xilinx Res. Labs., San Jose, CA, USA
pp. 75-80

Facilitating reuse in hardware models with enhanced type inference (PDF)

M. Vachharajani , Dept. of Comput. Sci. & Electr. Eng., Princeton Univ., NJ, USA
N. Vachharajani , Dept. of Comput. Sci. & Electr. Eng., Princeton Univ., NJ, USA
S. Malik , Dept. of Comput. Sci. & Electr. Eng., Princeton Univ., NJ, USA
D.I. August , Dept. of Comput. Sci. & Electr. Eng., Princeton Univ., NJ, USA
pp. 86-91

System-on-chip validation using UML and CWL (PDF)

Q. Zhu , Fujitsu Labs. LTD., Kawasaki, Japan
R. Oishi , Fujitsu Labs. LTD., Kawasaki, Japan
pp. 92-97

Compiler-directed code restructuring for reducing data TLB energy (PDF)

M. Kandemir , Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
pp. 98-103

Dynamic overlay of scratchpad memory for energy minimization (PDF)

M. Verma , Dept. of Comput. Sci., Dortmund Univ., Germany
L. Wehmeyer , Dept. of Comput. Sci., Dortmund Univ., Germany
P. Marweclel , Dept. of Comput. Sci., Dortmund Univ., Germany
pp. 104-109

CPU scheduling for statistically-assured real-time performance and improved energy efficiency (PDF)

Haisang Wu , Dept. of Electr. & Comput. Eng., Virginia Tech, Blacksburg, VA, USA
B. Ravindran , Dept. of Electr. & Comput. Eng., Virginia Tech, Blacksburg, VA, USA
pp. 110-115

Power-performance trade-offs for reconfigurable computing (PDF)

J. Noguera , Dept. of R&D, Hewlett-Packard, San Cugat Del Valles, Spain
pp. 116-121

Efficient search space exploration for HW-SW partitioning (PDF)

S. Banerjee , Center for Embedded Comput. Syst., California Univ., Irvine, CA, USA
N. Dutt , Center for Embedded Comput. Syst., California Univ., Irvine, CA, USA
pp. 122-127

Energy-efficient flash-memory storage systems with an interrupt-emulation mechanism (PDF)

Chin-Hsien Wu , Dept. of Comput. Sci. & Inf. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Tei-Wei Kuo , Dept. of Comput. Sci. & Inf. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Chia-Lin Yang , Dept. of Comput. Sci. & Inf. Eng., Nat. Taiwan Univ., Taipei, Taiwan
pp. 134-139

Memory system design space exploration for low-power, real-time speech recognition (PDF)

Rajeev Krishna , Adv. Comput. Archit. Lab., Michigan Univ., Ann Arbor, MI, USA
S. Mahlke , Adv. Comput. Archit. Lab., Michigan Univ., Ann Arbor, MI, USA
T. Austin , Adv. Comput. Archit. Lab., Michigan Univ., Ann Arbor, MI, USA
pp. 140-145

Analytical models for leakage power estimation of memory array structures (PDF)

M. Mamidipaka , Center for Embedded Comput. Syst., California Univ., Irvine, CA, USA
pp. 146-151

A timing-accurate HW/SW cosimulation of an ISS with SystemC (PDF)

L. Formaggio , Dipt. cli Informatica, Verona Univ., Italy
F. Fummi , Dipt. cli Informatica, Verona Univ., Italy
G. Pravadelli , Dipt. cli Informatica, Verona Univ., Italy
pp. 152-157

RTOS-centric hardware/software cosimulator for embedded system design (PDF)

S. Honda , Dept. of Inf. & Comput. Sci., Toyohashi Univ. of Technol., Japan
T. Wakabayashi , Dept. of Inf. & Comput. Sci., Toyohashi Univ. of Technol., Japan
pp. 158-163

Fast cosimulation of transformative systems with OS support on SMP computer (PDF)

Zhengting He , Dept. of Elec. & Comput. Eng., Texas Univ., Austin, TX, USA
A. Mok , Dept. of Elec. & Comput. Eng., Texas Univ., Austin, TX, USA
pp. 164-169

Power-aware communication optimization for networks-on-chips with voltage scalable links (PDF)

Dongkun Shin , Sch. of Comput. Sci. & Eng., Seoul Nat. Univ., South Korea
Jihong Kim , Sch. of Comput. Sci. & Eng., Seoul Nat. Univ., South Korea
pp. 170-175

Reducing power and latency in 2-D mesh NoCs using globally pseudochronous locally synchronous clocking (PDF)

E. Nilsson , Lab. of Electron. & Comput. Syst., R. Inst. of Technol., Kista, Sweden
J. Oberg , Lab. of Electron. & Comput. Syst., R. Inst. of Technol., Kista, Sweden
pp. 176-181

Multi-objective mapping for mesh-based NoC architectures (PDF)

G. Ascia , Dipt. di Ingegneria Informatica e delle Telecomunicazioni, Catania Univ., Italy
V. Catania , Dipt. di Ingegneria Informatica e delle Telecomunicazioni, Catania Univ., Italy
M. Palesi , Dipt. di Ingegneria Informatica e delle Telecomunicazioni, Catania Univ., Italy
pp. 182-187

Optimizing the memory bandwidth with loop fusion (PDF)

P. Marchal , IMEC/KULEUVEN, Heverlee, Belgium
F. Catthoor , IMEC/KULEUVEN, Heverlee, Belgium
pp. 188-193

Operation tables for scheduling in the presence of incomplete bypassing (PDF)

A. Shrivastavai , Sch. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA
N. Dutti , Sch. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA
A. Nicolaut , Sch. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA
pp. 194-199

A novel deadlock avoidance algorithm and its hardware implementation (PDF)

Jaehwan Lee , Georgia Inst. of Technol., Atlanta, GA, USA
V.J. Mooney , Georgia Inst. of Technol., Atlanta, GA, USA
pp. 200-205

Design and programming of embedded multiprocessors: an interface-centric approach (PDF)

P. van der Wolf , Philips Res., Eindhoven, Netherlands
E. de Kock , Philips Res., Eindhoven, Netherlands
T. Henriksson , Philips Res., Eindhoven, Netherlands
W. Kruijtzer , Philips Res., Eindhoven, Netherlands
G. Essink , Philips Res., Eindhoven, Netherlands
pp. 206-217

Low energy security optimization in embedded cryptographic systems (PDF)

C.H. Gebotys , Dept of Elec. & Comp. Eng., Waterloo Univ., Ont., Canada
pp. 224-229

Analyzing heap error behavior in embedded JVM environments (PDF)

G. Chen , Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
M. Kandemir , Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
N. Vijaykrishnan , Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
A. Sivasubramaniam , Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
M.J. Irwin , Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
pp. 230-235

Power analysis of system-level on-chip communication architectures (PDF)

K. Lahiri , NEC Labs. America, Princeton, NJ, USA
A. Raghunathan , NEC Labs. America, Princeton, NJ, USA
pp. 236-241

Fast exploration of bus-based on-chip communication architectures (PDF)

S. Pasricha , Center for Embedded Comput. Syst., California Univ., Irvine, CA, USA
N. Dutt , Center for Embedded Comput. Syst., California Univ., Irvine, CA, USA
pp. 242-247

Efficient exploration of on-chip bus architectures and memory allocation (PDF)

Sungchan Kim , Sch. of Electr. Eng. & Comput. Sci., Seoul Nat. Univ., South Korea
Chaeseok Im , Sch. of Electr. Eng. & Comput. Sci., Seoul Nat. Univ., South Korea
Soonhoi Ha , Sch. of Electr. Eng. & Comput. Sci., Seoul Nat. Univ., South Korea
pp. 248-253

Notes (PDF)

pp. 257

Notes (PDF)

pp. 258
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