The Community for Technology Leaders
Hardware/Software Co-Design, International Workshop on (2002)
Estes Park, Colorado
May 6, 2002 to May 8, 2002
ISBN: 1-58113-542-4
TABLE OF CONTENTS
Session 1: Advances in System Specification and System Design Frameworks

Codesign-Extended Applications (Abstract)

Frank Vahid , University of Califomia, Riverside; UC Irvine
Greg Stitt , University of Califomia, Riverside
Brian Grattan , University of Califomia, Riverside
pp. 1

Algorithmic Transformation Techniques for Efficient Exploration of Alternative Application Instances (Abstract)

Ed Deprettere , Leiden University, The Netherlands
Todor Stefanov , Leiden University, The Netherlands
Bart Kienhuis , Leiden University, The Netherlands
pp. 7

Concurrent Execution Semantics and Sequential Simulation Algorithms for the Metropolis Meta-Model (Abstract)

Felice Balarin , Cadence Berkeley Labs, CA
Alberto Sangiovanni-Vincentelli , University of California, Berkeley
Guang Yang , University of Massachusetts, Amherst
Claudio Passerone , Politecnico di Torino, Italy
Luciano Lavagno , Cadence Berkeley Labs, CA
Yosinori Watanabe , Cadence Berkeley Labs, CA
pp. 13

The Design Context of Concurrent Computation Systems (Abstract)

Donald E. Thomas , Carnegie Mellon University, Pittsburgh, PA
Christopher M. Eatedali , Carnegie Mellon University, Pittsburgh, PA
JoAnn M. Paul , Carnegie Mellon University, Pittsburgh, PA
pp. 19

A Language for Multiple Models of Computation (Abstract)

Johan Lilius , Turku Centre for Computer Science (TUCS), Finland
Dag Bj?rklund , Turku Centre for Computer Science (TUCS), Finland
pp. 25
Session 2: System Design Methods: Analysis and Verification

FPGA Resource and Timing Estimation from Matlab Execution Traces (Abstract)

Per Bjur?us , Saab Avionics, Sweden
Mikael Millberg , Royal Institute of Technology, Sweden
Axel Jantsch , Royal Institute of Technology, Sweden
pp. 31

Worst-Case Performance Analysis of Parallel, Communicating Software Processes* (Abstract)

O. Bringmann , FZI Forschungszentrum Informatik, Germany
A. Siebenborn , FZI Forschungszentrum Informatik, Germany
W. Rosenstiel , Universit?t T?bingen, Germany
pp. 37

Symbolic Model Checking of Dual Transition Petri Nets (Abstract)

Luis A. Cort? , Link?ping University, Sweden
Bashir M. Al-Hashimi , University of Southampton, UK
Mauricio Varea , University of Southampton, UK
Zebo Peng , Link?ping University, Sweden
Petru Eles , Link?ping University, Sweden
pp. 43

Simulation Bridge: A Framework for Multi-Processor Simulation (Abstract)

B. S. Sheshadri Chakravarthy , Texas Instruments India Ltd., Bangalore, India
G. D. Nagendra , Texas Instruments India Ltd., Bangalore, India
V. G. Prem Kumar , Texas Instruments India Ltd., Bangalore, India
pp. 49
Session 3: Design Space Exploration and Architectural Design of HW/SW Systems

Metrics for Design Space Exploration of Heterogeneous Multiprocessor Embedded Systems (Abstract)

Luigi Pomante , Politecnico di Milano, Italy
Donatella Sciuto , Politecnico di Milano, Italy
Fabio Salice , Politecnico di Milano, Italy
William Fornaciari , Politecnico di Milano, Italy
pp. 55

Fast Processor Core Selection for WLAN Modem using Mappability Estimation (Abstract)

Yang Qu , VTT Electronics, Oulu, Finland
Martti Forsell , VTT Electronics, Oulu, Finland
Jari Kreku , VTT Electronics, Oulu, Finland
Juha-Pekka Soininen , VTT Electronics, Oulu, Finland
pp. 61

Multi-Objective Design Space Exploration Using Genetic Algorithms (Abstract)

Tony Givargis , UC Irvine, CA
Maurizio Palesi , University of Catania, Italy
pp. 67

Scratchpad Memory : A Design Alternative for Cache On-chip Memory in Embedded Systems (Abstract)

Bo-Sik Lee , University of Dortmund, Germany
Peter Marwedel , University of Dortmund, Germany
Stefan Steinke , University of Dortmund, Germany
M. Balakrishnan , Indian Institute of Technology, Delhi
Rajeshwari Banakar , Indian Institute of Technology, Delhi
pp. 73

Hardware Support for Real-Time Embedded Multiprocessor System-on-a-Chip Memory Management (Abstract)

Mohamed Shalan , Georgia Institute of Technology, Atlanta
Vincent J. Mooney III , Georgia Institute of Technology, Atlanta
pp. 79

Large Exploration for HW/SW partitioning of Multirate and Aperiodic Real-Time Systems (Abstract)

Abdenour Azzedine , Universit? de Bretagne SUD, France
Jean-Philippe Diguet , Universit? de Bretagne SUD, France
Jean-Luc Philippe , Universit? de Bretagne SUD, France
pp. 85
Session 4: Co-Design Architecture and Synthesis

Program Slicing for Codesign (Abstract)

Jeffry T. Russell , University of Texas at Austin
pp. 91

Compiler-directed Customization of ASIP Cores (Abstract)

Rajeev Barua , University of Maryland, College Park
T. Vinod Kumar Gupta , University of Maryland, College Park
Roberto E. Ko , Cornell University, Ithaca, NY
pp. 97

A Study of CodePack: Optimizing Embedded Code Space (Abstract)

Avishay Orpaz , Tel Aviv University, Israel
Shlomo Weiss , Tel Aviv University, Israel
pp. 103

A Novel Codesign Approach based on Distributed Virtual Machines (Abstract)

Egon Teiniker , Graz University of Technology, Austriaj
Christian Steger , Graz University of Technology, Austriaj
Reinhold Weiss , Graz University of Technology, Austriaj
Christian Kreiner , Graz University of Technology, Austriaj
pp. 109
Session 5: System Partitioning and Timing Analysis

Transformation of SDL Specifications for System-Level Timing Analysis (Abstract)

Rafik Henia , Technical University of Braunschweig, Germany
Kai Richter , Technical University of Braunschweig, Germany
Rolf Ernst , Technical University of Braunschweig, Germany
Marek Jersak , Technical University of Braunschweig, Germany
Frank Slomka , University of Paderborn, Germany
pp. 121

A Strongly Polynomial-Time Algorithm for Over-Constraint Resolution (Abstract)

Ali Dasdan , Synopsys, Inc., Mountain View, CA
pp. 127

Hardware-Software Cosynthesis of Multi-Mode Multi-Task Embedded Systems with Real-Time Constraints (Abstract)

Hyunok Oh , Seoul National University, Korea
Soonhoi Ha , Seoul National University, Korea
pp. 133

Design of Multi-Tasking Coprocessor Control for Eclipse (Abstract)

Martijn J. Rutten , Philips Research Laboratories, The Netherlands
Jos. T. J. van Eijndhoven , Philips Research Laboratories, The Netherlands
Evert-Jan D. Pol , Philips Semiconductors, The Netherlands
pp. 139

Hardware-Software Bipartitioning for Dynamically Reconfigurable Systems, (Abstract)

Daler N. Rakhmatov , University of Arizona, Tucson
Sarma B. K. Vrudhula , University of Arizona, Tucson
pp. 145

HW/SW Partitioning and Code Generation of Embedded Control Applications on a Reconfigurable Architecture Platform (Abstract)

Alberto Sangiovanni-Vincentelli , PARADES EEIG, Rome, Italy; University of California, Berkeley
Yunjian Jiang , University of California, Berkeley
Massimo Baleani , PARADES EEIG, Rome, Italy
Robert K. Brayton , University of California, Berkeley
Yatish Patel , University of California, Berkeley
Frank Gennari , University of California, Berkeley
pp. 151
Session 6: Energy Efficiency in System Design

Energy Savings Through Compression in Embedded Java Environments (Abstract)

G. Chen , Pennsylvania State University, University Park
M. Kandemir , Pennsylvania State University, University Park
W. Wolf , Princeton University, NJ
N. Vijaykrishnan , Pennsylvania State University, University Park
M. J. Irwin , Pennsylvania State University, University Park
pp. 163

Communication Speed Selection for Embedded Systems with Networked Voltage-Scalable Processors (Abstract)

Pai H. Chou , University of California, Irvine
Nader Bagherzadeh , University of California, Irvine
Jinfeng Liu , University of California, Irvine
pp. 169

Pruning-Based Energy-Optimal Device Scheduling for Hard Real-Time Systems (Abstract)

Vishnu Swaminathan , Duke University, Durham, NC
Krishnendu Chakrabarty , Duke University, Durham, NC
pp. 175

Energy Frugal Tags in Reprogrammable I-Caches for Application-Specific Embedded Processors (Abstract)

Alex Orailoglu , University of California at San Diego
Peter Petrov , University of California at San Diego
pp. 181
Session 7: System Design Methods: Scheduling Advances

Holistic Scheduling and Analysis of Mixed Time/Event-Triggered Distributed Embedded Systems (Abstract)

Traian Pop , Link?ping University, Sweden
Petru Eles , Link?ping University, Sweden
Zebo Peng , Link?ping University, Sweden
pp. 187

Locality-Conscious Process Scheduling in Embedded Systems (Abstract)

G. Chen , Pennsylvania State University, University Park
M. Kandemir , Pennsylvania State University, University Park
I. Kolcu , UMIST, Manchester, UK
I. Kadayif , Pennsylvania State University, University Park
pp. 193

Reconfigurable SoC Design with Hierarchical FSM and Synchronous Dataflow Model (Abstract)

Sungjoo Yoo , SLS Group, TIMA Lab, France
Kiyoung Choi , Seoul National Univ., Korea
Sunghyun Lee , Seoul National Univ., Korea
pp. 199

Dynamic Run-Time HW/SW Scheduling Techniques for Reconfigurable Architectures (Abstract)

Rosa M. Badia , Technical University of Catalonia (UPC)
Juanjo Noguera , Hewlett-Packard InkJet Commercial Division (ICD)
pp. 205

Extended Quasi-Static Scheduling for Formal Synthesis and Code Generation of Embedded Software (Abstract)

Feng-Shi Su , National Chung Cheng University, Taiwan
Pao-Ann Hsiung , National Chung Cheng University, Taiwan
pp. 211

Authors Index (PDF)

pp. 217
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