The Community for Technology Leaders
Hardware/Software Co-Design, International Workshop on (2001)
Estes Park, Colorado
Apr. 25, 2001 to Apr. 27, 2001
ISBN: 1-58113-364-2
TABLE OF CONTENTS
Invited Talks
System Modeling and Specification

The Usage of Stochastic Processes in Embedded System Specifications (Abstract)

Axel Jantsch , Royal Institute of Technology, Stockhom, Sweden
Ingo Sander , Royal Institute of Technology, Stockhom, Sweden
Wenbiao Wu , Royal Institute of Technology, Stockhom, Sweden
pp. 5

Modeling and Evaluation of Hardware/Software Designs (Abstract)

Neal K. Tibrewala , Carnegie Mellon University, Pittsburgh, PA
JoAnn M. Paul , Carnegie Mellon University, Pittsburgh, PA
Donald E. Thomas , Carnegie Mellon University, Pittsburgh, PA
pp. 11

SystemC: A Homogenous Environment to Test Embedded Systems (Abstract)

Alessandro Fin , Universit? di Verona, Italy
Franco Fummi , Universit? di Verona, Italy
Maurizio Martignano , Sitek S.p.A., Verona, Italy
Mirko Signoretto , Universit? di Verona, Italy
pp. 17

Embedded UML: a Merger of Real-Time UML and Co-Design (Abstract)

Grant Martin , Cadence Design Systems, Inc., San Jose, CA
Luciano Lavagno , Cadence Design Systems, Inc., Berkeley, CA
Jean Louis-Guerin , Cadence Design Systems, Inc., France
pp. 23
Hardware/Software Partitioning and Design Environments

Hardware / Software Partitioning of Embedded System in OCAPI-xl (Abstract)

G. Vanmeerbeeck , IMEC vzw, Leuven, Belgium
P. Schaumont , IMEC vzw, Leuven, Belgium
S. Vernalde , IMEC vzw, Leuven, Belgium
M. Engels , IMEC vzw, Leuven, Belgium
I. Bolsens , IMEC vzw, Leuven, Belgium
pp. 30

HW/SW Partitioning of an Embedded Instruction Memory Decompressor (Abstract)

Shlomo Weiss , Tel Aviv University, Israel
Shay Beren , Tel Aviv University, Israel
pp. 36

A Practical Tool Box for System Level Communication Synthesis (Abstract)

Denis Hommais , Universit? Pierre et Marie Curie, Paris, France
Fr?d?ric P?trot , Universit? Pierre et Marie Curie, Paris, France
Ivan Aug? , Universit? Pierre et Marie Curie, Paris, France
pp. 48

System Canvas: A New Design Environment for Embedded DSP and Telecommunication Systems (Abstract)

Praveen K. Murthy , Angeles Design Systems, San Jose, CA
Etan G. Cohen , Angeles Design Systems, San Jose, CA
Steve Rowland , Angeles Design Systems, San Jose, CA
pp. 54
Architectures for Co-Design

Designing Domain-Specific Processors (Abstract)

Marnix Arnold , Delft University of Technology
Henk Corporaal , IMEC Leuven
pp. 61

RS-FDRA: A Register Sensitive Software Pipelining Algorithm for Embedded VLIW Processors (Abstract)

Cagdas Akturan , The University of Texas at Austin
Margarida F. Jacome , The University of Texas at Austin
pp. 67

A Novel Parallel Deadlock Detection Algorithm and Architecture (Abstract)

Pun H. Shiu , Georgia Institute of Technology
YuDong Tan , Georgia Institute of Technology
Vincent J. Mooney III , Georgia Institute of Technology
pp. 73

Towards Effective Embedded Processors in Codesigns: Customizable Partitioned Caches (Abstract)

Peter Petrov , University of California at San Diego
Alex Orailoglu , University of California at San Diego
pp. 79
Design Space Exploration and Evaluation Techniques

Development Cost and Size Estimation Starting from High-Level Specifications (Abstract)

William Fornaciari , Politecnico di Milano, Italy
Fabio Salice , Politecnico di Milano, Italy
Umberto Bondi , Univ. of Lugano, Switzerland
Edi Magini , OMNITEL, Italy
pp. 86

Exploring Design Space of Parallel Realizations: MPEG-2 Decoder Case Study (Abstract)

Basant K. Dwivedi , Indian Institute of Technology Delhi, New Delhi, India
Jan Hoogerbrugge , Philips Research, Eindhoven, The Netherlands
Paul Stravers , Philips Research, Eindhoven, The Netherlands
M. Balakrishnan , Indian Institute of Technology Delhi, New Delhi, India
pp. 92

Source-Level Execution Time Estimation of C Programs (Abstract)

C. Brandolese , Politecnico di Milano, Italy
W. Fornaciari , Politecnico di Milano, Italy
F. Salice , Politecnico di Milano, Italy
D. Sciuto , Politecnico di Milano, Italy
pp. 98

Evaluating Register File Size in ASIP Design (Abstract)

Manoj Kumar Jain , Indian Institute of Technology Delhi, India
Lars Wehmeyer , University of Dortmund, Germany
Stefan Steinke , University of Dortmund, Germany
Peter Marwwedel , University of Dortmund, Germany
M. Balakrishnan , Indian Institute of Technology Delhi, India
pp. 109
Synthesis and Transformation Techniques

Generating Mixed Hardware/Software Systems from SDL Specifications (Abstract)

Frank Slomka , University of Erlangen-Nuremberg, Germany
Matthias D?rfel , University of Erlangen-Nuremberg, Germany
Ralf M?nzenberger , University of Erlangen-Nuremberg, Germany
pp. 116

Area-Efficient Buffer Binding based on a Novel Two-Part FIFO Structure (Abstract)

Kyoungseok Rha , Samsung Electronics Co., Ltd., Korea
Kiyoung Choi , Seoul National University, Korea
pp. 122

Deriving Hard Real-Time Embedded Systems Implementations Directly from SDL Specifications (Abstract)

J. M. Alvarez , University of Malaga
M. Diaz , University of Malaga
L. Llopis , University of Malaga
E. Pimentel , University of Malaga
J. M. Troya , University of Malaga
pp. 128

A Trace Transformation Technique for Communication Refinement (Abstract)

Paul Lieverse , Delft University of Technology, The Netherlands
Pieter van der Wolf , Phillips Research, Eindhoven, The Netherlands
Ed Deprettere , Leiden University, The Netherlands
pp. 134

A Systematic Approach to Software Peripherals for Embedded Systems (Abstract)

D. Lioupis , Riga Feraiou St., Patras, Greece
A. Papagiannis , Univ. of Patras, Greece
D. Psihogiou , Univ. of Patras, Greece
pp. 140
Scheduling Techniques

A Constraint-based Application Model and Scheduling Techniques far Power-Aware Systems (Abstract)

Jinfeng Liu , University of California at Irvine
Pai H. Chou , University of California at Irvine
Nader Bagherzadeh , University of California at Irvine
Fadi Kurdahi , University of California at Irvine
pp. 153

Scheduling-based Code Size Reduction in Processors with Indirect Addressing Mode (Abstract)

Sungtaek Lim , Dynalith Systems Co., Ltd., Korea
Jihong Kim , Seoul National University, Korea
Kiyoung Choi , Seoul National University, Korea
pp. 165
Parameterized System Design and Simulation Approaches

Parameterised System Design based on Genetic Algorithms (Abstract)

Giuseppe Ascia , Universit? di Catania, Italy
Vincenzo Catania , Universit? di Catania, Italy
Maurizio Palesi , Universit? di Catania, Italy
pp. 177

Minimizing System Modification in an Incremental Design Approach (Abstract)

Paul Pop , Link?ping University
Petru Eles , Link?ping University
Traian Pop , Link?ping University
Zebo Peng , Link?ping University
pp. 183

High-Level Architectural Co-Simulation using Esterel and C (Abstract)

Andre Chatelain , Motorola Inc.
Yves Mathys , Motorola Inc.
Giovanni Placido , Motorola Inc.
Alberto La Rosa , Politecnico di Torino
Luciano Lavagno , Politecnico di Torino
pp. 189

A Generic Wrapper Architecture for Multi-Processor SoC Cosimulation and Design (Abstract)

Sungjoo Yoo , SLS Group, TIMA Laboratory, France
Gabriela Nicolescu , SLS Group, TIMA Laboratory, France
Damien Lyonnard , SLS Group, TIMA Laboratory, France
Amer Baghdadi , SLS Group, TIMA Laboratory, France
Ahmed A. Jerraya , SLS Group, TIMA Laboratory, France
pp. 195

The TACO Protocol Processor Simulation Environment (Abstract)

Seppo Virtanen , Turku Centre for Computer Science (TUCS), Finland
Johan Lilius , Turku Centre for Computer Science (TUCS), Finland
pp. 201
Code Generation and Software Issues

Formal Synthesis and Code Generation of Embedded Real-Time Software (Abstract)

Pao-Ann Hsiung , National Chung Cheng University, Taiwan
pp. 208

Compiler-Directed Selection of Dynamic Memory Layouts (Abstract)

Mahmut Kandemir , Pennsylvania State University, University Park
Ismail Kadayif , Pennsylvania State University, University Park
pp. 219

Logic Optimization and Code Generation for Embedded Control Applications (Abstract)

Yunjian Jiang , University of California, Berkeley
Robert K. Brayton , University of California, Berkeley
pp. 225
Low Power Design

Dynamic I/O Power Management for Hard Real-Time Systems (Abstract)

Vishnu Swaminathan , Duke University, Durham
Krishnendu Chakrabarty , Duke University, Durham
S. S. Iyengar , Louisiana State University, Baton Rouge
pp. 237

Hybrid Global/Local Search Strategies for Dynamic Voltage Scaling in Embedded Multiprocessors (Abstract)

Neal K. Bambha , University of Maryland
Shuvra S. Bhattacharyya , University of Maryland
J? Teich , University of Paderborn, Germany
Eckart Zitzler , Swiss Federal Institute of Technology, Zurich, Switzerland
pp. 243

Processor Frequency Setting for Energy Minimization of Streaming Multimedia Application (Abstract)

Andrea Acquaviva , University of Bologna, Italy
Luca Benini , University of Bologna, Italy
Bruno Rocc? , University of Bologna, Italy
pp. 249

Retargetable Compilation for Low Power (Abstract)

Wen-Tsong Shiue , Silicon Metrics Corporation, Austin, TX
pp. 254

A Design Framework to Efficiently Explore Energy-Delay Tradeoffs (Abstract)

William Fornaciari , Politecnico di Milano, Italy
Donatella Sciuto , Politecnico di Milano, Italy
Cristina Silvano , Universit? degli Studi di Milano, Italy
Vittorio Zaccaria , Politecnico di Milano, Italy
pp. 260

Author Index (PDF)

pp. 269
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