The Community for Technology Leaders
Hardware/Software Co-Design, International Workshop on (2000)
San Diego, California
May 3, 2000 to May 5, 2000
ISBN: 1-58113-214-x
TABLE OF CONTENTS
Invited Talks
System Level Modeling and Integration

On the Roles of Functions and Objects in System Specification (Abstract)

Axel Jantsch , Royal Institute of Technology, Kista, Sweden
Ingo Sander , Royal Institute of Technology, Kista, Sweden
pp. 8

Compaan: Deriving Process Networks from Matlab for Embedded Signal Processing Architectures (Abstract)

Edwin Rijpkema , Leiden University, The Netherlands
Ed Deprettere , Leiden University, The Netherlands
Bart Kienhuis , UC Berkeley, CA
pp. 13

Modeling Industrial Embedded Systems with UML (Abstract)

Henrique D. Santos , Universidade do Minho, Braga, Portugal
Ricardo J. Machado , Universidade do Minho, Braga, Portugal
Jo?o M. Fernandes , Universidade do Minho, Braga, Portugal
pp. 18
Power Estimation

Energy Estimation for 32-bit Microprocessors (Abstract)

D. Sciuto , Politecnico di Milano, Italy
C. Brandolese , Politecnico di Milano, Italy
F. Salice , Politecnico di Milano, Italy
W. Fornaciari , Politecnico di Milano, Italy
pp. 24

Power Optimization of System-Level Address Buses based on Software Profiling (Abstract)

C. Silvano , Politecnico di Milano, Italy; CEFRIEL, Milano, Italy
M. Polentarutti , CEFRIEL, Milano, Italy
D. Sciuto , Politecnico di Milano, Italy; CEFRIEL, Milano, Italy
W. Fornaciari , Politecnico di Milano, Italy; CEFRIEL, Milano, Italy
pp. 29

Instruction-Level Power Estimation for Embedded VLIW Cores (Abstract)

C. Silvano , Politecnico di Milano, Italy
V. Zaccaria , Politecnico di Milano, Italy
M. Sami , Politecnico di Milano, Italy
D. Sciuto , Politecnico di Milano, Italy
pp. 34

Low-Power Task Scheduling for Multiple Devices (Abstract)

Yung-Hsiang Lu , Stanford University, CA
Giovanni De Micheli , Stanford University, CA
Luca Benini , Universit? di Bologna, Italy
pp. 39
Memory Estimation and Optimization

Co-Design of Interleaved Memory Systems (Abstract)

Wayne Wolf , Princeton University, NJ
Hua Lin , Princeton University, NJ
pp. 46

Memory Architecture for Efficient Utilization of SDRAM: A Case Study of the Computation/Memory Access Trade-Off (Abstract)

Hans Holten-Lund , Technical University of Denmark
Steen Pedersen , Technical University of Denmark
Thomas Gleerup , Technical University of Denmark
Jan Madsen , Technical University of Denmark
pp. 51

Storage Requirement Estimation for Data Intensive Applications with Partially Fixed Execution Ordering (Abstract)

Einar J. Aas , Norwegian University of Science and Technology, Trondheim, Norway
Per Gunnar Kjeldsberg , Norwegian University of Science and Technology, Trondheim, Norway
Francky Catthoor , IMEC, Leuven, Belgium; Dept. of Kath. Univ. Leuven
pp. 56
Performance Estimation and Timing Analysis

Performance Estimation for Embedded Systems with Data and Control Dependencies (Abstract)

Petru Eles , Link?ping University, Sweden
Zebo Peng , Link?ping University, Sweden
Paul Pop , Link?ping University, Sweden
pp. 62

Program Path Analysis to Bound Cache-Related Preemption Delay in Preemptive Real-Time Systems (Abstract)

Nikil D. Dutt , University of California, Irvine
Hiroyuki Tomiyama , University of California, Irvine
pp. 67

Fast Performance Prediction for Periodic Task Systems (Abstract)

Xiaobo (Sharon) Hu , University of Notre Dame, IN
Gang Quan , University of Notre Dame, IN
pp. 72

Performance Estimation of Multiple-Cache IP-based Systems: Case Study of an Interdependency Problem and Application of an Extended Shared Memory Model (Abstract)

Kyoungseok Rha , Seoul National University, Korea
Sungjoo Yoo , Seoul National University, Korea
Jinyong Jung , Seoul National University, Korea
Youngchul Cho , Seoul National University, Korea
Kiyoung Choi , Seoul National University, Korea
pp. 77

Software Performance Estimation Strategies in a System-Level Design Tool (Abstract)

Wido Krujitzer , Philips Research Laboratories
Jwahar R. Bammi , Cadence Design Systems
Mihai T. Lazarescu , Politecnico di Torino, Italy
Luciano Lavagno , Politecnico di Torino, Italy
Edwin Harcourt , Cadence Design Systems
pp. 82
IP Cores and Reuse Issues

A Method To Derive Application-Specific Embedded Processing Cores (Abstract)

Ivan C. Kraljic , MiroTech MicroSystems Inc. Saint-Laurent, Canada
Yvon Savaria , ?cole Polytechnique de Montr?al, Canada; MiroTech MicroSystems Inc. Saint-Laurent, Canada
Olivier H?bert , ?cole Polytechnique de Montr?al, Canada
pp. 88

Linking Codesign and Reuse in Embedded Systems Design (Abstract)

M. Meerwein , Robert Bosch Gmbh, Germany
C. Baumgartner , Robert Bosch Gmbh, Germany
W. Glauert , University of Erlangen-Nuremberg, Germany
pp. 93

Parameterized System Design (Abstract)

Frank Vahid , University of California, Riverside
Tony D. Givargis , University of California, Riverside
pp. 98

Extended Design Reuse Trade-Offs in Hardware-Software Architecture Mapping (Abstract)

D. Verkest , IMEC, Leuven, Belgium
F. Vermeulen , IMEC, Leuven, Belgium
H. De Man , IMEC, Leuven, Belgium
F. Catthoor , IMEC, Leuven, Belgium
pp. 103
Software Code Generation and Optimization

Task Response Time Optimization Using Cost-Based Operation Motion (Abstract)

Abdallah Tabbara , University of California at Berkeley
Bassam Tabbara , University of California at Berkeley
Alberto Sangiovanni-Vincentelli , University of California at Berkeley
pp. 110

Heuristic Tradeoffs between Latency and Energy Consumption in Register Assignment (Abstract)

R. Anand , University of Texas at Austin, TX
M. Jacome , University of Texas at Austin, TX
G. de Veciana , University of Texas at Austin, TX
pp. 115

Code Compression as a Variable in Hardware/Software Co-Design (Abstract)

Haris Lekatsas , Princeton University
Wayne Wolf , Princeton University
J? Henkel , NEC USA
pp. 120
SoC Design and Validation

A Generic Tool Set for Application Specific Processor Architectures (Abstract)

Frank Engel , Dresden University of Technology, Germany
Gerhard P. Fettweis , Dresden University of Technology, Germany
Johannes N?hrenberg , Dresden University of Technology, Germany
pp. 126

Frequency Interleaving as a Codesign Scheduling Paradigm (Abstract)

Donald E. Thomas , Carnegie Mellon University, Pittsburgh, PA
Simon N. Peffers , Carnegie Mellon University, Pittsburgh, PA
JoAnn M. Paul , Carnegie Mellon University, Pittsburgh, PA
pp. 131

Automatic Test Bench Generation for Simulation-based Validation (Abstract)

M. Sonza Reorda , DAI - Politecnico di Torino, Italy
M. Violante , DAI - Politecnico di Torino, Italy
M. Rebaudengo , DAI - Politecnico di Torino, Italy
L. Lavagno , Universit? di Udine, Italy
M. Lajolo , NEC C&C Research Labs, Princeton, NJ
pp. 136
Design Framework and Case Studies

Wireless Protocols Design: Challenges and Opportunities (Abstract)

A. Sangiovanni-Vincentelli , University of California at Berkeley
J. Rabaey , University of California at Berkeley
M. Sgroi , University of California at Berkeley
F. De Bernardinis , University of California at Berkeley
S. F. Li , University of California at Berkeley
J. L. da Silva Jr. , University of California at Berkeley
pp. 147

ASDEN: A Comprehensive Design Framework Vision for Automotive Electronic Control Systems (Abstract)

Daniel Dayton , JRS Research Laboratories Inc., Anaheim, California
R. Todd Hansell , Motorola Automotive and Industrial, Detroit, Michigan
Deborah Wilson , JRS Research Laboratories Inc., Anaheim, California
pp. 152

A Novel Codesign Methodology for Real-Time Embedded COTS Multiprocessor-Based Signal Processing Systems (Abstract)

Randall S. Janka , Georgia Institute of Technology, Atlanta
Linda M. Wills , Georgia Institute of Technology, Atlanta
pp. 157

ACM SIGDA (PDF)

pp. 163

ACM SIGSOFT (PDF)

pp. 164

Author Index (PDF)

pp. 167
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