The Community for Technology Leaders
Hardware/Software Co-Design, International Workshop on (1999)
Rome, Italy
May 3, 1999 to May 5, 1999
ISBN: 1-58113-132-1
TABLE OF CONTENTS
Application-Specific Instruction-Set Processor (ASIP) Design Issues

Development of an Optimizing Compiler for a Fujitsu Fixed-Point Digital Signal Processor (Abstract)

Ashok Sudarsanam , Department of Electrical Engineering, Princeton, NJ
Sreeranga P. Rajan , Fujitsu Laboratories of America, Sunnyvale, CA
Masahiro Fujita , Fujitsu Laboratories of America, Sunnyvale, CA
Sharad Malik , Department of Electrical Engineering, Princeton, NJ
pp. 2

Instruction Set Selection for ASIP Design (Abstract)

Michael Gschwind , IBM Thomas J. Watson Research Center, Yorktown Heights, NY
pp. 7

Resource Constrained Dataflow Retiming Heuristics for VLIW ASIPs (Abstract)

C. Akturan , University of Texas, Austin, TX
M. Jacome , University of Texas, Austin, TX
G. de Veciana , University of Texas, Austin, TX
pp. 12

An ASIP Design Methodology for Embedded Systems (Abstract)

Kayhan K???k?akar , Escalade Corporation, Santa Clara, CA
pp. 17

Automatic Detection of Recurring Operation Patterns (Abstract)

Henk Corporal , Delft University of Technology
Marnix Arnold , Delft University of Technology
pp. 22
Case Studies

An MPEG-2 Decoder Case Study as a Driver for a System Level Design Methodology (Abstract)

Mudit Goel , University of California, Berkeley
Paul Lieverse , Delft University of Technology, The Netherlands
Pieter van der Wolf , Philips Research Laboratories, The Netherlands
Kees Vissers , Philips Research Laboratories, The Netherlands
David La Hei , Philips Research Laboratories, The Netherlands
pp. 33

Timed Executable System Specification of an ADSL Modem using a C++ based Design Environment: A Case Study (Abstract)

Prabhat Avasare , IMEC, Leuven, Belgium
Michiel Esvelt , IMEC, Leuven, Belgium
Dirk Desmet , IMEC, Leuven, Belgium
Diederik Verkest , IMEC, Leuven, Belgium
Hugo De Man , IMEC, Leuven, Belgium
pp. 38

Flexible Design of SPARC Cores: a Quantitative Study (Abstract)

Antonio N? , University of Las Palmas de Gran Canaria, Canary Islands
Tom? Bautista , University of Las Palmas de Gran Canaria, Canary Islands
pp. 43

Hardware/Software Co-Design of an Avionics Communication Protocol Interface System: an Industrial Case Study (Abstract)

Daniel Esteve , ENSEEIHT, France
Yves Favard , AEROSPATIALE A?ronautique
Jean-No? Contensou , ENSEEIHT, France
Philippe Pons , AEROSPATIALE A?ronautique
Franqois Clout? , ENSEEIHT, France
Pascal Pampagnin , AEROSPATIALE A?ronautique
pp. 48
Codesign Methodologies

Multilanguage Design of Heterogeneous Systems (Abstract)

M. Romdhani , TIMA Laboratory, France
R. Suescun , TIMA Laboratory, France
A. A. Jerraya , TIMA Laboratory, France
P. Coste , TIMA Laboratory, France
F. Hessel , TIMA Laboratory, France
Ph. Le Marrec , TIMA Laboratory, France
N. Zergainoh , TIMA Laboratory, France
Z. Sugar , TIMA Laboratory, France
pp. 54

The Case for a Configure-and-Execute Paradigm (Abstract)

Frank Vahid , Univ. of California, Riverside
Tony Givargis , Univ. of California, Riverside
pp. 59

Designing Digital Video Systems: Modeling and Scheduling (Abstract)

Y. Watanabe , Cadence European Labs, Rome, Italy
W. J. M. Smits , Philips Research Labs, Eindhoven, Netherlands
A. L. Sangiovanni-Vincentelli , Cadence European Labs, Rome, Italy
H. J. H. N. Kenter , Philips Research Labs, Eindhoven, Netherlands
C. Passerone , Politecnico di Torino, Turin, Italy
pp. 64

Fast Prototyping: a Dystem Design Flow for Fast Design, Prototyping and Efficient IP Reuse (Abstract)

Francois Pogodalla , STMicroelectronics, France
Richard Hersemeule , STMicroelectronics, France
Pierre Coulomb , STMicroelectronics, France
pp. 69

Optimized Rapid Prototyping for Real-Time Embedded Heterogeneous Multiprocessors (Abstract)

Y. Sorel , INRIA-Rocquencourt Domaine de Voluceau, France
T. Grandpierre , INRIA-Rocquencourt Domaine de Voluceau, France
C. Lavarenne , INRIA-Rocquencourt Domaine de Voluceau, France
pp. 74

Using Codesign Techniques to Support Analog Functionality (Abstract)

Michael J. Knieser , Case Western Reserve University, Cleveland, OH
Chris A. Papachristou , Case Western Reserve University, Cleveland, OH
Dan J. Weyer , Case Western Reserve University, Cleveland, OH
Francis G. Wolff , Case Western Reserve University, Cleveland, OH
pp. 79
Hardware/Software Cosimulation and Timing Analysis

A Compilation-based Software Estimation Scheme for Hardware/Software Co-Simulation (Abstract)

Mihai Lazarescu , Politecnico di Torino, Italy
Marcello Lajolo , Politecnico di Torino, Italy
Alberto Sangiovanni-Vincentelli , University of California at Berkeley
pp. 85

A Probabilistic Performance Metric for Real-Time System Design (Abstract)

Edwin H.-M. Sha , University of Notre Dame, IN
Tao Zhou , University of Notre Dame, IN
Xiaobo(Sharon) Hu , University of Notre Dame, IN
pp. 90

Iterative Cache Simulation of Embedded CPUs with Trace Stripping (Abstract)

Wayne Wolf , Princeton University, NJ
Zhao Wu , Princeton University, NJ
pp. 95

Optimizing Geographically Distributed Timed Cosimulation by Hierarchically Grouped Messages (Abstract)

Kiyoung Choi , Seoul National University, Korea
Sungjoo Yoo , Seoul National University, Korea
pp. 100

Peer-based Multithreaded Executable Co-Specification (Abstract)

Sandra J. Weber , Carnegie Mellon University, Pittsburgh, PA
Simon N. Peffers , Carnegie Mellon University, Pittsburgh, PA
JoAnn M. Paul , Carnegie Mellon University, Pittsburgh, PA
Donald E. Thomas , Carnegie Mellon University, Pittsburgh, PA
pp. 105

Timing Coverification of Concurrent Embedded Real-Time Systems (Abstract)

Pao-Ann Hsiung , Academia Sinica, Taipei, Taiwan
pp. 110
Models for Codesign

A Unified Formal Model of ISA and FSMD (Abstract)

Daniel D. Gajski , University of California, Irvine
Jianwen Zhu , University of California, Irvine
pp. 121

Graph based Communication Analysis for Hardware/Software Codesign (Abstract)

Jan Madsen , Technical University of Denmark
Peter Voigt Knudsen , Technical University of Denmark
pp. 131

System Synthesis Utilizing a Layered Functional Model (Abstract)

Axel Jantsch , Royal Institute of Technology, Stockholm, Sweden
Ingo Sander , Royal Institute of Technology, Stockholm, Sweden
pp. 136
Software and Communication Issues

Communication Refinement in Video Systems on Ohio (Abstract)

H. J. H. N. Kenter , Philips Research Laboratories Eindhoven
W. M. Kruijtzer , Philips Research Laboratories Eindhoven
J.-Y. Brunel , Philips Research Laboratories Eindhoven
E. A. de Kock , Philips Research Laboratories Eindhoven
W. J. M. Smits , Philips Research Laboratories Eindhoven
pp. 142

Compiling Esterel into Sequential Code (Abstract)

Stephen A. Edwards , Synopsys, Inc., Mountain View, CA
pp. 147

Power Estimation for Architectural Exploration of HW/SW Communication on System-Level Buses (Abstract)

William Fornaciari , Politecnico di Milano, Italy
Cristina Silvano , CEFRIEL, Italy
Donatella Sciuto , Politecnico di Milano, Italy
pp. 152

Software Controlled Power Management (Abstract)

Yung-Hsiang Lu , Stanford University, CA
Tajana Simunic , Stanford University, CA
Giovanni De Micheli , Stanford University, CA
pp. 157

A Statechart based HW/SW Codesign System (Abstract)

D. J. Kinniment , University of Newcastle, UK
I. D. Bates , University of Newcastle, UK
E. G. Chester , University of Newcastle, UK
pp. 162
Synthesis, Scheduling and Partitioning

3D Exploration of Software Schedules for DSP Algorithms (Abstract)

E. Zitzler , ETH Z?rich, Switzerland
S. S. Bhattacharyya , University of Maryland, College Park
J. Teich , University of Paderborn, Germany
pp. 168

Scheduling Hardware/Software Systems using Symbolic Techniques (Abstract)

Lothar Thiele , Swiss Federal Institute of Technology (ETH), Switzerland
Rolf Ernst , Technical University of Braunschweig, Germany
Dirk Ziegenbein , Technical University of Braunschweig, Germany
J? Teich , University of Paderborn, Germany
pp. 173

Scheduling with Optimized Communication for Time-Triggered Embedded Systems (Abstract)

Zebo Peng , Link?ping University, Sweden
Paul Pop , Link?ping University, Sweden
Petru Eles , Link?ping University, Sweden
pp. 178

A Hardware-Software Cosynthesis Technique based on Heterogeneous Multiprocessor Scheduling (Abstract)

Soonhoi Ha , Seoul National University, Korea
Hyunok Oh , Seoul National University, Korea
pp. 183

Embedded System Synthesis under Memory Constraints (Abstract)

Peter Bj?rn-J?rgensen , Nokia Mobile Phones A/S, Copenhagen
Jan Madsen , Technical University of Denmark
pp. 188

Overhead Effects in Real-Time Preemptive Schedules (Abstract)

Wayne Wolf , Princeton University
David L. Rhodes , US Army CECOM/RDEC
pp. 193

System-Level Partitioning with Uncertainty (Abstract)

Carlos Frederico Cavalcanti , DCC - ICEx - UFMG, Brazil
Di?genes Cec?lio da Silva Jr. , DCC - ICEx - UFMG, Brazil
Claudionor Coelho Jr. , DCC - ICEx - UFMG, Brazil
Jones Albuguerque , DCC - ICEx - UFMG, Brazil
Ant?nio Ot?vio Fernandes , DCC - ICEx - UFMG, Brazil
pp. 198

Timing-Driven HW/SW Codesign based on Task Structuring and Process Timing Simulation (Abstract)

Rajesh Gupta , University of California, Irvine
Ali Dasdan , University of Illinois, Urbana
Dinesh Ramanathan , University of California, Irvine
pp. 203
Group Discussion Topic Summaries

Aspects on System-Level Design (PDF)

Erik Stoy , Ericsson Radio Systems AB, Stockholm, Sweden
Jonas Plantin , Ericsson Radio Systems AB, Stockholm, Sweden
pp. 209

How Standards will Enable Hardware/Software Co-Design (PDF)

Mark Genoe , Alcatel
Chris Lennard , Cadence
Joachim Kunkel , Synopsys
Shay Ben-Chorin , National
Brian Bailey , Mentor Graphics
Kamal Hashmi , Fujitsu-ICL
Grant Martin , Cadence
Gjalt de Jong , Alcatel
pp. 211

Author Index (PDF)

pp. 213
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