The Community for Technology Leaders
Hardware/Software Co-Design, International Workshop on (1996)
Pittsburgh, Pennsylvania
Mar. 18, 1996 to Mar. 20, 1996
ISBN: 0-8186-7243-9
TABLE OF CONTENTS

Committees (PDF)

pp. ix
Session 1: Transformation Based Co-Design and Communication Synthesis

A Multi-Level Transformation Approach to HW/SW Codesign: A Case Study (Abstract)

Tommy King-Yin Cheung , University of New South Wales
Graham Hellestrand , University of New South Wales
Prasert Kanthamanon , University of New South Wales
pp. 10

Fully Parallel Hardware/Software Codesign for Multi-Dimensional DSP Applications (Abstract)

Michael Sheliga , University of Notre Dame
Edwin Hsing-Mean S' ha , University of Notre Dame
Nelson Luiz Passos , University of Notre Dame
pp. 18
Session 2: Estimation Techniques 1

A Co-Design Methodology Based on Formal Specification and High-level Estimation (Abstract)

L. Sanchez , ETSIT, Universidad Politecnica de Madrid
C. Delgado-Kloos , ETSIT, Universidad Politecnica de Madrid
J. C. Lopez , ETSIT, Universidad Politecnica de Madrid
N. Martinez , Universidad Carlos III de Madrid
C. Carreras , ETSIT, Universidad Politecnica de Madrid
M. L. Lopez , ETSIT, Universidad Politecnica de Madrid
pp. 28

Speed-up estimation for HW/SW-systems (Abstract)

W. Hardt , Paderborn Univ., Germany
W. Rosenstiel , Paderborn Univ., Germany
pp. 36

A framework for interactive analysis of timing constraints in embedded systems (Abstract)

R.K. Gupta , Dept. of Comput. Sci., Illinois Univ., Urbana, IL, USA
pp. 44

The Interplay of Run-Time Estimation and Granularity in HW/SW Partitioning (Abstract)

Joerg Henkel , Technische Universitat Braunschweig
Rolf Ernst , Technische Universitat Braunschweig
pp. 52
Session 3: Partitioning and Clustering

Partitioning and Exploration Strategies in the TOSCA Co-Design Flow (Abstract)

A. Balboni , ITALTEL-SIT, Central Research Labs, CLTE
W. Fornaciari , Politecnico di Milano, Dip. Elettronica e Informazione
D. Sciuto , Politecnico di Milano, Dip. Elettronica e Informazione
pp. 62

Two-level Partitioning of Image Processing Algorithms for the Parallel Map-oriented Machine (Abstract)

Reiner W. Hartenstein , University of Kaiserslautern
Juergen Becker , University of Kaiserslautern
Rainer Kress , University of Kaiserslautern
pp. 77

PACE: A Dynamic Programming Algorithm for Hardware/Software Partitioning (Abstract)

Peter Voigt Knudsen , Technical University of Denmark
Jan Madsen , Technical University of Denmark
pp. 85
Session 4: Case Studies

A Model for the Coanalysis of Hardware and Software Architectures (Abstract)

Sanjaya Kumar , 3660 Technology Drive, Minneapolis, MN 55418
John Shackleton , 3660 Technology Drive, Minneapolis, MN 55418
Fred Rose , 3660 Technology Drive, Minneapolis, MN 55418
Todd Steeves Honeywell , 3660 Technology Drive, Minneapolis, MN 55418
Todd Carpenter , 3660 Technology Drive, Minneapolis, MN 55418
pp. 94

A Case Study in Co-Design of Communication Controllers (Abstract)

R. Gerndt , Institut fuer angewandte Mikroelektronik
pp. 104
Topic 1: Representation Issues in Co-Design
Open Poster Session

Towards a Model for Hardware and Software Functional Partitioning (Abstract)

Thuy DM Le , University of California, Riverside
Frank Vahid , University of California, Riverside
pp. 116

Implications of Codesign as a Natural Constituent of a Systems Engineering Discipline for Computer Based Systems (Abstract)

Markus Voss , Universitaet Karlsruhe Institut fuer Mikrorechner und Automation (IMA)
Oliver Hammerschmidt , Universitaet Karlsruhe Institut fuer Mikrorechner und Automation (IMA)
pp. 124

Uninterpreted Co-Simulation for Performance Evaluation of Hw/Sw Systems (Abstract)

Jean Paul Calvez , IRESTE, University of NANTES, La Chantrerie, CP3003
Olivier Pasquier , IRESTE, University of NANTES, La Chantrerie, CP3003
Dominique Heller , IRESTE, University of NANTES, La Chantrerie, CP3003
pp. 132
Rump Session

Author Index (PDF)

pp. 141
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