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2010 IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) (2010)
Scottsdale, AZ
Oct. 24, 2010 to Oct. 29, 2010
ISBN: 978-1-6055-8905-3
TABLE OF CONTENTS

Intermediate fabrics: Virtual architectures for circuit portability and fast placement and routing (Abstract)

J Coole , Dept. of Electr. & Comput. Eng., Univ. of Florida, Gainesville, FL, USA
G Stitt , Dept. of Electr. & Comput. Eng., Univ. of Florida, Gainesville, FL, USA
pp. 13-22

Verification of dynamically reconfigurable embedded systems by model transformation rules (Abstract)

F Madlener , Integrated Circuits & Syst. Lab., Tech. Univ. Darmstadt, Darmstadt, Germany
J Weingart , Integrated Circuits & Syst. Lab., Tech. Univ. Darmstadt, Darmstadt, Germany
S A Huss , Integrated Circuits & Syst. Lab., Tech. Univ. Darmstadt, Darmstadt, Germany
pp. 33-40

Hardware/software optimization of error detection implementation for real-time embedded systems (Abstract)

A Lifa , Linkoping Univ., Linköping, Sweden
P Eles , Linkoping Univ., Linköping, Sweden
Zebo Peng , Linkoping Univ., Linköping, Sweden
V Izosimov , Embedded Intell. Solutions, Linköping, Sweden
pp. 41-50

Scheduling garbage collection in real-time systems (Abstract)

M Kero , Dept. of Comput. Sci., Lulea Univ. of Technol., Luleå, Sweden
S Aittamaa , Dept. of Comput. Sci., Lulea Univ. of Technol., Luleå, Sweden
pp. 51-60

Hardware/software co-design for high performance computing: Challenges and opportunities (Abstract)

X S Hu , Dept. of Comput. Sci. & Eng., Univ. of Notre Dame, Notre Dame, IN, USA
R C Murphy , Scalable Comput. Archit. Dept., Sandia Nat. Labs., Albuquerque, NM, USA
S Dosanjh , Comput. & Software Syst. Dept., Sandia Nat. Labs., Albuquerque, NM, USA
K Olukotun , Dept. of Electr. Eng., Stanford Univ., Stanford, CA, USA
S Poole , Comput. Sci. Div., Oak Ridge Nat. Lab., Oak Ridge, TN, USA
pp. 63-64

Exploring programming model-driven QoS support for NoC-based platforms (Abstract)

J Joven , LSI, EPFL, Lausanne, Switzerland
A Marongiu , DEIS, Univ. of Bologna, Bologna, Italy
F Angiolini , iNoCs SaRL, Lausanne, Switzerland
L Benini , DEIS, Univ. of Bologna, Bologna, Italy
G De Micheli , LSI, EPFL, Lausanne, Switzerland
pp. 65-74

Optimal synthesis of latency and throughput constrained pipelined MPSoCs targeting streaming applications (Abstract)

H Javaid , Sch. of Comput. Sci. & Eng., Univ. of New South Wales, Sydney, NSW, Australia
Xin He , Sch. of Comput. Sci. & Eng., Univ. of New South Wales, Sydney, NSW, Australia
A Ignjatovic , Sch. of Comput. Sci. & Eng., Univ. of New South Wales, Sydney, NSW, Australia
S Parameswaran , Sch. of Comput. Sci. & Eng., Univ. of New South Wales, Sydney, NSW, Australia
pp. 75-84

OE+IOE: A novel turn model based fault tolerant routing scheme for networks-on-chip (Abstract)

S Pasricha , Dept. of Electr. & Comput. Eng., Colorado State Univ., Fort Collins, CO, USA
Yong Zou , Dept. of Electr. & Comput. Eng., Colorado State Univ., Fort Collins, CO, USA
D Connors , Dept. of Electr. Eng., Univ. of Colorado Denver, Denver, CO, USA
H J Siegel , Dept. of Electr. & Comput. Eng., Colorado State Univ., Fort Collins, CO, USA
pp. 85-93

Worst-case performance analysis of Synchronous Dataflow scenarios (Abstract)

Marc Geilen , Eindhoven Univ. of Technol., Den Dolech, Netherlands
S Stuijk , Eindhoven Univ. of Technol., Den Dolech, Netherlands
pp. 125-134

Improving platform-based system synthesis by satisfiability modulo theories solving (Abstract)

F Reimann , Univ. of Erlangen-Nuremberg, Erlangen, Germany
M Glass , Univ. of Erlangen-Nuremberg, Erlangen, Germany
C Haubelt , Univ. of Erlangen-Nuremberg, Erlangen, Germany
M Eberl , Univ. of Erlangen-Nuremberg, Erlangen, Germany
J Teich , Univ. of Erlangen-Nuremberg, Erlangen, Germany
pp. 135-144

A case for lifetime-aware task mapping in embedded chip multiprocessors (Abstract)

A S Hartman , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
D E Thomas , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
B H Meyer , Dept. of Comput. Sci., Univ. of Virginia, Charlottesville, VA, USA
pp. 145-154

Automatic Memory Partitioning: Increasing memory parallelism via data structure partitioning (Abstract)

Y Ben Asher , Comput. Sci. Dept., Haifa Univ., Haifa, Israel
N Rotem , Comput. Sci. Dept., Haifa Univ., Haifa, Israel
pp. 155-161

An introduction to the SystemC synthesis subset standard (Abstract)

P Coussy , Univ. de Bretagne-Sud, Lorient, France
A Takach , Mentor Graphics, Wilsonville, OR, USA
M McNamara , Cadence, San Jose, CA, USA
M Meredith , Forte Design Syst., Redmond, WA, USA
pp. 183-184

Embedded tutorial — Compilation techniques for CGRAs: Exploring all parallelization approaches (Abstract)

T Vander Aa , Imec, Leuven, Belgium
P Raghavan , Imec, Leuven, Belgium
S Mahlke , Univ. of Michigan, Ann Arbor, MI, USA
B De Sutter , Ghent Univ., Ghent, Belgium
A Shrivastava , Arizona State Univ., Tempe, AZ, USA
F Hannig , Univ. of Erlangen, Nuremberg, Germany
pp. 185-186

Dynamic, non-linear cache architecture for power-sensitive mobile processors (Abstract)

G Bournoutian , Univ. of California, San Diego, La Jolla, CA, USA
A Orailoglu , Univ. of California, San Diego, La Jolla, CA, USA
pp. 187-194

A greedy buffer allocation algorithm for power-aware communication in body sensor networks (Abstract)

H Ghasemzadeh , Dept. of Electr. Eng., Univ. of Texas at Dallas, Richardson, TX, USA
R Jafari , Dept. of Electr. Eng., Univ. of Texas at Dallas, Richardson, TX, USA
pp. 195-204

A holistic approach to Network-on-Chip synthesis (Abstract)

G Leary , Dept. of CSE, Arizona State Univ., Tempe, AZ, USA
K S Chatha , Dept. of CSE, Arizona State Univ., Tempe, AZ, USA
pp. 213-222

NeuroNoC: Neural network inspired runtime adaptation for an on-chip communication architecture (Abstract)

T Ebi , Dept. of Embedded Syst., Karlsruhe Inst. of Technol. (KIT), Karlsruhe, Germany
M A A Faruque , Dept. of Embedded Syst., Karlsruhe Inst. of Technol. (KIT), Karlsruhe, Germany
Jörg Henkel , Dept. of Embedded Syst., Karlsruhe Inst. of Technol. (KIT), Karlsruhe, Germany
pp. 223-230

Workload characterization and its impact on multicore platform design (Abstract)

P Bogdan , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
R Marculescu , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 231-240

parSC: Synchronous parallel SystemC simulation on multi-core host architectures (Abstract)

C Schumacher , Inst. for Integrated Signal Process. Syst., RWTH Aachen Univ., Aachen, Germany
R Leupers , Inst. for Integrated Signal Process. Syst., RWTH Aachen Univ., Aachen, Germany
D Petras , Synopsys, Inc., Aachen, Germany
A Hoffmann , Synopsys, Inc., Aachen, Germany
pp. 241-246

FastFwd: An efficient hardware acceleration technique for trace-driven network-on-chip simulation (Abstract)

G Krishnaiah , Dept. of CSE, IIT Delhi, New Delhi, India
B V N Silpa , Dept. of CSE, IIT Delhi, New Delhi, India
P R Panda , Dept. of CSE, IIT Delhi, New Delhi, India
A Kumar , Dept. of CSE, IIT Delhi, New Delhi, India
pp. 247-256

Automatic parallelization of embedded software using hierarchical task graphs and integer linear programming (Abstract)

D Cordes , Inf. Centrum Dortmund, Dortmund, Germany
P Marwedel , Inf. Centrum Dortmund, Dortmund, Germany
A Mallik , Imec Belgium, Leuven, Belgium
pp. 267-276

Performance modeling of embedded applications with zero architectural knowledge (Abstract)

M Lattuada , Dipt. di Elettron. e Inf., Politec. di Milano, Milan, Italy
F Ferrandi , Dipt. di Elettron. e Inf., Politec. di Milano, Milan, Italy
pp. 277-286

A performance model and code overlay generator for scratchpad enhanced embedded processors (Abstract)

M A Baker , Comput. Sci. & Eng. Dept., Arizona State Univ., Tempe, AZ, USA
A Panda , Comput. Sci. & Eng. Dept., Arizona State Univ., Tempe, AZ, USA
N Ghadge , Comput. Sci. & Eng. Dept., Arizona State Univ., Tempe, AZ, USA
A Kadne , Comput. Sci. & Eng. Dept., Arizona State Univ., Tempe, AZ, USA
K S Chatha , Comput. Sci. & Eng. Dept., Arizona State Univ., Tempe, AZ, USA
pp. 287-296

Unconventional fabrics, architectures, and models for future multi-core systems (Abstract)

R Marculescu , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
C Teuscher , Dept. of Electr. & Comput. Eng., Portland State Univ., Portland, OR, USA
P P Pande , Sch. of Electr. Eng. & Comput. Sci., Washington State Univ., Pullman, WA, USA
pp. 327-328

Modeling and analyzing real-time multiprocessor systems (Abstract)

M Wiggers , Dept. of EEMCS, Univ. of Twente, Enschede, Netherlands
L Thiele , Comput. Eng. & Networks Lab., ETH Zurich, Zurich, Switzerland
E A Lee , Dept. of EECS, Univ. of California, Berkeley, CA, USA
S Schliecker , Tech. Univ., Braunschweig, Germany
M Bekooij , NXP Semicond., Eindhoven, Netherlands
pp. 329-330

Exploring models of computation with Ptolemy II (Abstract)

C Brooks , EECS Dept., Univ. of California, Berkeley, Berkeley, CA, USA
E A Lee , EECS Dept., Univ. of California, Berkeley, Berkeley, CA, USA
S Tripakis , EECS Dept., Univ. of California, Berkeley, Berkeley, CA, USA
pp. 331-332
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