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2007 5th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) (2007)
Salzburg
Sept. 30, 2007 to Oct. 3, 2007
ISBN: 978-1-5959-3824-4
TABLE OF CONTENTS

Simultaneous synthesis of buses, data mapping and memory allocation for MPSoC (Abstract)

B H Meyer , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
D E Thomas , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 3-8

A framework for rapid system-level exploration, synthesis, and programming of multimedia MP-SoCs (Abstract)

Mark Thompson , Dept. of Comput. Sci., Univ. of Amsterdam, Amsterdam, Netherlands
Hristo Nikolov , Leiden Embedded Res. Center, Leiden Univ., Leiden, Netherlands
Todor Stefanov , Leiden Embedded Res. Center, Leiden Univ., Leiden, Netherlands
Andy D Pimentel , Dept. of Comput. Sci., Univ. of Amsterdam, Amsterdam, Netherlands
Cagkan Erbas , Dept. of Comput. Sci., Univ. of Amsterdam, Amsterdam, Netherlands
Simon Polstra , Dept. of Comput. Sci., Univ. of Amsterdam, Amsterdam, Netherlands
E F Deprettere , Leiden Embedded Res. Center, Leiden Univ., Leiden, Netherlands
pp. 9-14

Synchronization after design refinements with sensitive delay elements (Abstract)

T Raudvere , R. Inst. of Technol., Stockholm, Sweden
I Sander , R. Inst. of Technol., Stockholm, Sweden
A Jantsch , R. Inst. of Technol., Stockholm, Sweden
pp. 21-26

Embedded software development on top of transaction-level models (Abstract)

W Klingauf , Dept. E.I.S., Tech. Univ. of Braunschweig, Braunschweig, Germany
Robert Günzel , Dept. E.I.S., Tech. Univ. of Braunschweig, Braunschweig, Germany
Christian Schröder , Dept. E.I.S., Tech. Univ. of Braunschweig, Braunschweig, Germany
pp. 27-32

Pointer re-coding for creating definitive MPSoC models (Abstract)

P Chandraiah , Center for Embedded Comput. Syst., Univ. of California, Irvine, CA, USA
R Domer , Center for Embedded Comput. Syst., Univ. of California, Irvine, CA, USA
pp. 33-38

Dynamic security domain scaling on symmetric multiprocessors for future high-end embedded systems (Abstract)

H Inoue , Syst. IP Core Res. Labs., NEC Corp., Sagamihara, Japan
A Ikeno , NEC Informatec Syst., Ltd., Kawasaki, Japan
T Abe , Syst. IP Core Res. Labs., NEC Corp., Sagamihara, Japan
J Sakai , Syst. IP Core Res. Labs., NEC Corp., Sagamihara, Japan
M Edahiro , Syst. IP Core Res. Labs., NEC Corp., Sagamihara, Japan
pp. 39-44

A smart random code injection to mask power analysis based side channel attacks (Abstract)

J A Ambrose , Univ. of New South Wales, Sydney, NSW, Australia
R G Ragel , Univ. of New South Wales, Sydney, NSW, Australia
S Parameswaran , Univ. of New South Wales, Sydney, NSW, Australia
pp. 51-56

Ensuring secure program execution in multiprocessor embedded systems: A case study (Abstract)

K Patel , Sch. of Comput. Sci. & Eng., Univ. of New South Wales, Sydney, NSW, Australia
S Parameswaran , Sch. of Comput. Sci. & Eng., Univ. of New South Wales, Sydney, NSW, Australia
S L Shee , Sch. of Comput. Sci. & Eng., Univ. of New South Wales, Sydney, NSW, Australia
pp. 57-62

Combined approach to system level performance analysis of embedded systems (Abstract)

S Kunzli , Technol. Group, Switzerland
A Hamann , Tech. Univ. Braunschweig, Braunschweig, Germany
R Ernst , Tech. Univ. Braunschweig, Braunschweig, Germany
L Thiele , ETH Zurich, Zürich, Switzerland
pp. 63-68

Event-based re-training of statistical contention models for heterogeneous multiprocessors (Abstract)

A Bobrek , ECE Dept., Carnegie Mellon Univ., Pittsburgh, PA, USA
J M Paul , ECE Dept., Virginia Tech, Blacksburg, VA, USA
D E Thomas , ECE Dept., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 69-74

HySim: A fast simulation framework for embedded software development (Abstract)

S Kraemer , Inst. for Integrated Signal Process. Syst., RWTH Aachen Univ., Aachen, Germany
L Gao , Inst. for Integrated Signal Process. Syst., RWTH Aachen Univ., Aachen, Germany
J Weinstock , Inst. for Integrated Signal Process. Syst., RWTH Aachen Univ., Aachen, Germany
R Leupers , Inst. for Integrated Signal Process. Syst., RWTH Aachen Univ., Aachen, Germany
G Ascheid , Inst. for Integrated Signal Process. Syst., RWTH Aachen Univ., Aachen, Germany
H Meyr , Inst. for Integrated Signal Process. Syst., RWTH Aachen Univ., Aachen, Germany
pp. 75-80

A computational reflection mechanism to support platform debugging in SystemC (Abstract)

B Albertini , Inst. of Comput., Unicamp, Campinas, Brazil
S Rigo , Inst. of Comput., Unicamp, Campinas, Brazil
G Araujo , Inst. of Comput., Unicamp, Campinas, Brazil
C Araujo , Inf. Center, UFPE, Recife, Brazil
E Barros , Inf. Center, UFPE, Recife, Brazil
W Azevedo , Inf. Center, UFPE, Recife, Brazil
pp. 81-86

Thread warping: A framework for dynamic synthesis of thread accelerators (Abstract)

G Stitt , Dept. of Electr. & Comput. Eng., Univ. of Florida, Gainesville, FL, USA
F Vahid , Dept. of Comput. Sci. & Eng., Univ. of California, Riverside, CA, USA
pp. 93-98

HW/SW co-design for Esterel processing (Abstract)

S Gadtke , Dept. of Comput. Sci., Christian-Albrechts-Univ. zu Kiel, Kiel, Germany
C Traulsen , Dept. of Comput. Sci., Christian-Albrechts-Univ. zu Kiel, Kiel, Germany
R von Hanxleden , Dept. of Comput. Sci., Christian-Albrechts-Univ. zu Kiel, Kiel, Germany
pp. 99-104

Temperature-aware processor frequency assignment for MPSoCs using convex optimization (Abstract)

S Murali , LSI, EPFL, Lausanne, Switzerland
A Mutapcic , Dept. of Electr. Eng., Stanford Univ., Stanford, CA, USA
D Atienza , LSI, EPFL, Lausanne, Switzerland
R Gupta , Dept. of Comput. Sci. & Eng., UCSD, La Jolla, CA, USA
S Boyd , Dept. of Electr. Eng., Stanford Univ., Stanford, CA, USA
G De Micheli , LSI, EPFL, Lausanne, Switzerland
pp. 111-116

Locality optimization in wireless applications (Abstract)

J Absar , IMEC, KU LEUVEN, Leuven, Belgium
A Lambrechts , IMEC, KU LEUVEN, Leuven, Belgium
Min Li , IMEC, KU LEUVEN, Leuven, Belgium
M Jayapala , IMEC, Leuven, Belgium
P Raghavan , IMEC, KU LEUVEN, Leuven, Belgium
A Vandecappelle , IMEC, Leuven, Belgium
pp. 125-130

A code-generator generator for Multi-Output Instructions (Abstract)

H Scharwaechter , Integrated Signal Process. Syst., RWTH Aachen Univ., Aachen, Germany
R Leupers , Integrated Signal Process. Syst., RWTH Aachen Univ., Aachen, Germany
G Ascheid , Integrated Signal Process. Syst., RWTH Aachen Univ., Aachen, Germany
H Meyr , Integrated Signal Process. Syst., RWTH Aachen Univ., Aachen, Germany
J M Youn , Software Optimization & Restructuring, Res. Group, Seoul Nat. Univ., Seoul, South Korea
Yunheung Paek , Software Optimization & Restructuring, Res. Group, Seoul Nat. Univ., Seoul, South Korea
pp. 131-136

Influence of procedure cloning on WCET prediction (Abstract)

P Lokuciejewski , Comput. Sci. 12, Univ. of Dortmund, Dortmund, Germany
H Falk , Comput. Sci. 12, Univ. of Dortmund, Dortmund, Germany
M Schwarzer , Comput. Sci. 12, Univ. of Dortmund, Dortmund, Germany
P Marwedel , Comput. Sci. 12, Univ. of Dortmund, Dortmund, Germany
H Theiling , AbsInt Angewandte Inf., Saarbrücken, Germany
pp. 137-142

Compile-time decided instruction cache locking using worst-case execution paths (Abstract)

H Falk , Comput. Sci. 12, Univ. of Dortmund, Dortmund, Germany
S Plazar , Comput. Sci. 12, Univ. of Dortmund, Dortmund, Germany
H Theiling , AbsInt Angewandte Inf., Saarbrucken, Germany
pp. 143-148

Channel trees: Reducing latency by sharing time slots in time-multiplexed Networks on Chip (Abstract)

A Hansson , Electron. Syst. Group, Eindhoven Univ. of Technol., Eindhoven, Netherlands
M Coenen , Corp. Res. Dept., NXP Semicond., Eindhoven, Netherlands
K Goossens , Corp. Res. Dept., NXP Semicond., Eindhoven, Netherlands
pp. 149-154

Performance and resource optimization of NoC router architecture for master and slave IP cores (Abstract)

G Leary , Dept. of CSE, Arizona State Univ., Tempe, AZ, USA
K Mehta , Dept. of CSE, Arizona State Univ., Tempe, AZ, USA
K S Chatha , Dept. of CSE, Arizona State Univ., Tempe, AZ, USA
pp. 155-160

A data protection unit for NoC-based architectures (Abstract)

Leandro Fiorin , Fac. of Inf., Univ. of Lugano, Lugano, Switzerland
Gianluca Palermo , Dipt. di Elettron. e Inf., Politec. di Milano, Milan, Italy
Slobodan Lukovic , Fac. of Inf., Univ. of Lugano, Lugano, Switzerland
Cristina Silvano , Dipt. di Elettron. e Inf., Politec. di Milano, Milan, Italy
pp. 167-172

Complex task activation schemes in system level performance analysis (Abstract)

W Haid , Comput. Eng. & Networks Lab., ETH Zurich, Zurich, Switzerland
L Thiele , Comput. Eng. & Networks Lab., ETH Zurich, Zurich, Switzerland
pp. 173-178

Improved response time analysis of tasks scheduled under preemptive Round-Robin (Abstract)

R Racu , Inst. of Comput. & Commun. Network Eng., Tech. Univ. of Braunschweig, Braunschweig, Germany
Li Li , Inst. of Comput. & Commun. Network Eng., Tech. Univ. of Braunschweig, Braunschweig, Germany
R Henia , Inst. of Comput. & Commun. Network Eng., Tech. Univ. of Braunschweig, Braunschweig, Germany
A Hamann , Inst. of Comput. & Commun. Network Eng., Tech. Univ. of Braunschweig, Braunschweig, Germany
R Ernst , Inst. of Comput. & Commun. Network Eng., Tech. Univ. of Braunschweig, Braunschweig, Germany
pp. 179-184

Probabilistic performance risk analysis at system-level (Abstract)

A Viehl , FZI Forschungszentrum Inf., Karlsruhe, Germany
M Schwarz , FZI Forschungszentrum Inf., Karlsruhe, Germany
O Bringmann , FZI Forschungszentrum Inf., Karlsruhe, Germany
W Rosenstiel , FZI Forschungszentrum Inf., Karlsruhe, Germany
pp. 185-190

ESL design and HW/SW co-verification of high-end Software Defined Radio platforms (Abstract)

A C H Ng , IMEC, Leuven, Belgium
J W Weijers , IMEC, Leuven, Belgium
M Glassee , IMEC, Leuven, Belgium
T Schuster , IMEC, Leuven, Belgium
B Bougard , IMEC, Leuven, Belgium
L Van der Perre , IMEC, Leuven, Belgium
pp. 191-196

Smart driver for power reduction in next generation bistable electrophoretic display technology (Abstract)

M A Baker , CSE Dept., Arizona State Univ., Tempe, AZ, USA
A Shrivastava , CSE Dept., Arizona State Univ., Tempe, AZ, USA
K S Chatha , CSE Dept., Arizona State Univ., Tempe, AZ, USA
pp. 197-202

On the impact of manufacturing process variations on the lifetime of sensor networks (Abstract)

S Garg , Carnegie Mellon Univ., Pittsburgh, PA, USA
D Marculescu , Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 203-208

Performance modeling for early analysis of multi-core systems (Abstract)

R Bergamaschi , IBM T. J. Watson Res. Center, Yorktown Heights, NY, USA
I Nair , IBM T. J. Watson Res. Center, Yorktown Heights, NY, USA
G Dittmann , IBM T. J. Watson Res. Center, Yorktown Heights, NY, USA
H Patel , Virginia Tech, Blacksburg, VA, USA
G Janssen , IBM T. J. Watson Res. Center, Yorktown Heights, NY, USA
N Dhanwada , IBM EDA, East Fishkill, NY, USA
A Buyuktosunoglu , IBM T. J. Watson Res. Center, Yorktown Heights, NY, USA
E Acar , IBM Austin Res., Austin, TX, USA
G Nam , IBM Austin Res., Austin, TX, USA
G Han , Univ. of California, Los Angeles, CA, USA
D Kucar , IBM T. J. Watson Res. Center, Yorktown Heights, NY, USA
P Bose , IBM T. J. Watson Res. Center, Yorktown Heights, NY, USA
J Darringer , IBM T. J. Watson Res. Center, Yorktown Heights, NY, USA
pp. 209-214

Bridging gap between simulation and spreadsheet study (Abstract)

A Perrin , STMicroeletronics, Grenoble, France
F Ghenassia , STMicroeletronics, Grenoble, France
pp. 215-216

Performance analysis and design space exploration for high-end biomedical applications: Challenges and solutions (Abstract)

Iyad Al Khatib , R. Inst. of Technol., IMIT, Sweden
Davide Bertozzi , ENDIF, Univ. of Ferrara, Ferrara, Italy
Axel Jantsch , R. Inst. of Technol., IMIT, Sweden
Luca Benini , DEIS, Univ. of Bologna, Bologna, Italy
pp. 217-226

A low power VLIW processor generation method by means of extracting non-redundant activation conditions (Abstract)

H Iwato , Grad. Sch. of Inf. Sci. & Technol., Osaka Univ., Suita, Japan
K Sakanushi , Grad. Sch. of Inf. Sci. & Technol., Osaka Univ., Suita, Japan
Y Takeuchi , Grad. Sch. of Inf. Sci. & Technol., Osaka Univ., Suita, Japan
M Imai , Grad. Sch. of Inf. Sci. & Technol., Osaka Univ., Suita, Japan
pp. 227-232

Scheduling and voltage scaling for energy/reliability trade-offs in fault-tolerant time-triggered embedded systems (Abstract)

P Pop , Inf. & Math. Modelling Dept., Tech. Univ. of Denmark, Lyngby, Denmark
K H Poulsen , Inf. & Math. Modelling Dept., Tech. Univ. of Denmark, Lyngby, Denmark
V Izosimov , Comput. & Inf. Sci. Dept., Linkoping Univ., Linköping, Sweden
P Eles , Comput. & Inf. Sci. Dept., Linkoping Univ., Linköping, Sweden
pp. 233-238

Reliable multiprocessor system-on-chip synthesis (Abstract)

Changyun Zhu , ECE Dept., Queen's Univ., Kingston, ON, Canada
Zhenyu Gu , EECS Dept., Northwestern Univ., Evanston, IL, USA
R P Dick , EECS Dept., Northwestern Univ., Evanston, IL, USA
Li Shang , ECE Dept., Queen's Univ., Kingston, ON, Canada
pp. 239-244

Predator: A predictable SDRAM memory controller (Abstract)

B Akesson , Tech. Univ., Eindhoven, Netherlands
K Goossens , NXP Semicond. Res., Delft Univ. of Technol., Delft, Netherlands
M Ringhofer , Graz Univ. of Technol., Graz, Austria
pp. 251-256

Performance improvement of block based NAND flash translation layer (Abstract)

S Choudhuri , Center for Embedded Comput. Syst., Univ. of California, Irvine, CA, USA
T Givargis , Center for Embedded Comput. Syst., Univ. of California, Irvine, CA, USA
pp. 257-262
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