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2005 Third IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS'05) (2005)
Jersey City, NJ, USA
Sept. 19, 2005 to Sept. 21, 2005
ISBN: 1-59593-161-9
TABLE OF CONTENTS

Hardware and software architectures for the CELL processor (PDF)

Michael Day , IBM Systems&Technology Group, Austin, TX
Peter Hofstee , IBM Systems&Technology Group, Austin, TX
pp. 1

Performance and power analysis of computer systems (PDF)

Trevor Mudge , University of Michigan, Ann Arbor, MI
pp. 2

Future processors: flexible and modular (PDF)

Jeff Welser , IBM, Rochester, MN
Charlie Johnson , IBM, Rochester, MN
pp. 4-6

Future wireless convergence platforms (PDF)

Mayan Moudgill , Sandbridge Technologies, Inc., White Plains, NY
Michael Schulte , Sandbridge Technologies, Inc., White Plains, NY
Stamatis Vassiliadis , Sandbridge Technologies, Inc., White Plains, NY
Daniel Iancu , Sandbridge Technologies, Inc., White Plains, NY
Gary Nacer , Sandbridge Technologies, Inc., White Plains, NY
Michael Samori , Sandbridge Technologies, Inc., White Plains, NY
Sanjay Jintukar , Sandbridge Technologies, Inc., White Plains, NY
Stuart Stanley , Sandbridge Technologies, Inc., White Plains, NY
Tanuj Raja , Sandbridge Technologies, Inc., White Plains, NY
John Glossner , Sandbridge Technologies, Inc., White Plains, NY
pp. 7-12

A core flight software system (PDF)

Jonathan Wilmot , Goddard Space Flight Center, Greenbelt, MD
pp. 13-14

Conflict analysis in multiprocess synthesis for optimized system integration (Abstract)

Wolfgang Rosenstiel , Universitat Tubingen, Tubingen, Germany
Axel Siebenborn , Microelectronic System Design, Karlsruhe, Germany
Oliver Bringmann , Microelectronic System Design, Karlsruhe, Germany
pp. 15-20

A cycle-accurate compilation algorithm for custom pipelined datapaths (PDF)

Daniel Gajski , University of California Irvine
Mehrdad Reshadi , University of California Irvine
pp. 21-26

Highly flexible multi-mode system synthesis (PDF)

John Lach , University of Virginia, Charlottesville, VA
Vinu Vijay Kumar , Texas Instruments, Stafford, TX
pp. 27-32

Energy-efficient address translation for virtual memory support in low-power and real-time embedded processors (PDF)

Peter Petrov , University of Maryland, College Park, MD
Xiangrong Zhou , University of Maryland, College Park, MD
pp. 33-38

Automated data cache placement for embedded VLIW ASIPs (PDF)

Richard Taylor , CriticalBlue Ltd, Edinburgh, UK
Barry O'Rourke , CriticalBlue Ltd, Edinburgh, UK
George Bruce , CriticalBlue Ltd, Edinburgh, UK
Japheth Hossell , CriticalBlue Ltd, Edinburgh, UK
Paul Morgan , CriticalBlue Ltd, Edinburgh, UK
pp. 39-44

An efficient direct mapped instruction cache for application-specific embedded systems (PDF)

Chuanjun Zhang , University of Missouri-Kansas City, Kansas City, MO
pp. 45-50

Shift buffering technique for automatic code synthesis from synchronous dataflow graphs (PDF)

Nikil Dutt , University of California Irvine, CA
Soonhoi Ha , Seoul National University, Seoul, Korea
Hyunok Oh , University of California Irvine, CA
pp. 51-56

Implementation of dynamic streaming Applications on heterogeneous multi-Processor architectures (PDF)

Pieter Van Der Wolf , Philips Research, Eindhoven, The Netherlands
Jeffrey Kang , Philips Research, Eindhoven, The Netherlands
Tomas Henriksson , Philips Research, Eindhoven, The Netherlands
pp. 57-62

Using minimal minterms to represent programmability (PDF)

Kurt Keutzer , University of California, Berkeley
Scott J. Weber , University of California, Berkeley
pp. 63-68

Key research problems in NoC design: a holistic perspective (PDF)

Radu Marculescu , Carnegie Mellon University, Pittsburgh, PA
Jingcao Hu , Carnegie Mellon University, Pittsburgh, PA
Umit Y. Ogras , Carnegie Mellon University, Pittsburgh, PA
pp. 69-74

A unified approach to constrained mapping and routing on network-on-chip architectures (PDF)

Kees Goossens , Philips Research Laboratories, Eindhoven, The Netherlands
Andrei Radulescu , Philips Research Laboratories, Eindhoven, The Netherlands
Andreas Hansson , Lund University, Lund, Sweden
pp. 75-80

Spatial division multiplexing: a novel approach for guaranteed throughput on NoCs (PDF)

P. Marchal , IMEC vzw, Kapeldreef 75, Leuven, Belgium
D. Verkest , IMEC vzw, Kapeldreef 75, Leuven, Belgium
A. Shickova , IMEC vzw, Kapeldreef 75, Leuven, Belgium
F. Catthoor , IMEC vzw, Kapeldreef 75, Leuven, Belgium
F. Robert , IMEC vzw, Kapeldreef 75, Leuven, Belgium
A. Leroy , IMEC vzw, Kapeldreef 75, Leuven, Belgium
pp. 81-86

Increasing on-chip memory space utilization for embedded chip multiprocessors through data compression (PDF)

Mahmut Kandemir , Pennsylvania State University
Mary Jane Irwin , Pennsylvania State University
Ozcan Ozturk , Pennsylvania State University
pp. 87-92

CRAMES: compressed RAM for embedded systems (PDF)

Haris Lekatsas , NEC Laboratories America, Princeton, NJ
Robert P. Dick , Northwestern University, Evanston, IL
Srimat Chakradhar , NEC Laboratories America, Princeton, NJ
Lei Yang , Northwestern University, Evanston, IL
pp. 93-98

Efficient behavior-driven runtime dynamic voltage scaling policies (PDF)

Margaret Martonosi , Princeton University, Princeton, NJ
Sharad Malik , Princeton University, Princeton, NJ
Fen Xie , Princeton University, Princeton, NJ
pp. 105-110

A system-level methodology for fully compensating process variability impact of memory organizations in periodic applications (PDF)

H. Wang , IMEC vzw, Leuven, Belgium
M. Miranda , IMEC vzw, Leuven, Belgium
F. Lobmaier , IMEC vzw, Leuven, Belgium
F. Catthoor , IMEC vzw, Leuven, Belgium
A. Papanikolaou , IMEC vzw, Leuven, Belgium
pp. 117-122

What will system level design be when it grows up? (PDF)

Patrick Lysaght , Xilinx Research
Peter Marwedel , University of Dortmund, Germany
Mike Muller , ARM, UK
Daniel Gajski , UC Irvine
David Goodwin , Tensilica
Grant Martin , Tensilica
pp. 123

The design of a smart imaging core for automotive and consumer applications: a case study (Abstract)

Ghiath Alkadi , Philips Research, The Netherlands
Victor Reyes , University of Las Palmas GC, Spain
Bruno Steux , Ecole des Mines de Paris, France
Jorn Jochalsky , University of Hannover, Germany
Thomas Hinz , Philips Semiconductors Hamburg, Germany
Winfried Gehrke , Philips Semiconductors Hamburg, Germany
Wido Kruijtzer , Philips Research, The Netherlands
pp. 124-129

Microcoded coprocessor for embedded secure biometric authentication systems (PDF)

Ingrid Verbauwhede , UCLA, Los Angeles, CA
Patrick Schaumont , UCLA, Los Angeles, CA
Shenglin Yang , UCLA, Los Angeles, CA
pp. 130-135

An architectural level design methodology for embedded face detection (PDF)

R. Chellappa , Princeton Univ., Princeton, NJ
S. S. Bhattacharyya , Princeton Univ., Princeton, NJ
S. Saha , Princeton Univ., Princeton, NJ
W. Wolf , Univ. of Maryland, College Park, MD
G. Aggarwal , Princeton Univ., Princeton, NJ
J. Schlessman , Univ. of Maryland, College Park, MD
V. Kianzad , Princeton Univ., Princeton, NJ
pp. 136-141

A power estimation methodology for systemC transaction level models (PDF)

Vijay Narayanan , Pennsylvania State University, University Park, PA
Ing-chao Lin , Pennsylvania State University, University Park, PA
Nagu Dhanwada , Hopewell Junction, NY
pp. 142-147

Aggregating processor free time for energy reduction (PDF)

Alex Nicolau , University of California, Irvine, CA
Nikil Dutt , University of California, Irvine, CA
Eugene Earlie , Intel Corporation
Aviral Shrivastava , University of California, Irvine, CA
pp. 154-159

Enhanced code density of embedded CISC processors with echo technology (PDF)

Mauricio Breternitz , Intel Labs, Clara, CA
Herbert Hum , Intel Labs, Clara, CA
Ramesh Peri , Intel Labs, Clara, CA
Jay Pickett , Intel Labs, Clara, CA
Youfeng Wu , Intel Labs, Clara, CA
pp. 160-165

Satisfying real-time constraints with custom instructions (PDF)

Tulika Mitra , National University of Singapore, Republic of Singapore
Pan Yu , National University of Singapore, Republic of Singapore
pp. 166-171

An integer linear programming approach for identifying instruction-set extensions (PDF)

Can Ozturan , Bogazici University, Turkey
Gunhan Dundar , Bogazici University, Turkey
Kubilay Atasu , Bogazici University, Turkey
pp. 172-177

FIDES: an advanced chip multiprocessor platform for secure next generation mobile terminals (PDF)

Masaki Kondo , NEC Informatec Systems, Ltd. , Kanagawa, Japan
Masato Edahiro , NEC Corporation, Kanagawa, Japan
Akihisa Ikeno , NEC Informatec Systems, Ltd. , Kanagawa, Japan
Junji Sakai , NEC Corporation, Kanagawa, Japan
Hiroaki Inoue , NEC Corporation, Kanagawa, Japan
pp. 178-183

Power-smart system-on-chip architecture for embedded cryptosystems (PDF)

H. Vahedi , University of Guelph, Guelph, Canada
S. Gregori , University of Guelph, Guelph, Canada
Y. Zhanrong , University of Guelph, Guelph, Canada
R. Muresan , University of Guelph, Guelph, Canada
pp. 184-189

Enhancing security through hardware-assisted run-time validation of program data properties (PDF)

Anand Raghunathan , NEC Laboratories America, Princeton, NJ
Niraj K. Jha , Princeton University, Princeton, NJ
Srivaths Ravi , NEC Laboratories America, Princeton, NJ
Divya Arora , Princeton University, Princeton, NJ
pp. 190-195

System-level design automation tools for digital microfluidic biochips (PDF)

Fei Su , Duke University, Durham, NC
Krishnendu Chakrabarty , Duke University, Durham, NC
pp. 201-206

Blue matter on blue gene/L: massively parallel computation for biomolecular simulation (PDF)

Frank Suits , IBM Thomas J. Watson Research Center, Yorktown Heights, NY
Maria Eleftheriou , IBM Thomas J. Watson Research Center, Yorktown Heights, NY
Mark Giampapa , IBM Thomas J. Watson Research Center, Yorktown Heights, NY
Aleksandr Rayshubskiy , IBM Thomas J. Watson Research Center, Yorktown Heights, NY
Blake Fitch , IBM Thomas J. Watson Research Center, Yorktown Heights, NY
Michael C. Pitman , IBM Thomas J. Watson Research Center, Yorktown Heights, NY
T.J. Christopher Ward , IBM Hursley Park, Hursley, UK
Robert S. Germain , IBM Thomas J. Watson Research Center, Yorktown Heights, NY
pp. 207-212

High-level synthesis for large bit-width multipliers on FPGAs: a case study (PDF)

James P. Davis , University of South Carolina, Columbia, SC
Duncan A. Buell , University of South Carolina, Columbia, SC
Siddhaveerasharan Devarkal , University of South Carolina, Columbia, SC
Gang Quan , University of South Carolina, Columbia, SC
pp. 213-218

Power optimization for universal hash function data path using divide-and-concatenate technique (PDF)

Ramesh Karri , Polytechnic University, Brooklyn, NY
Bo Yang , Polytechnic University, Brooklyn, NY
pp. 219-224

Efficient performance analysis of asynchronous systems based on periodicity (PDF)

Steven M. Nowick , Columbia University, New York, NY
E. G. Coffman , Columbia University, New York, NY
Peggy B. McGee , Columbia University, New York, NY
pp. 225-230

SOMA: a tool for synthesizing and optimizing memory accesses in ASICs (PDF)

Seth Copen Goldstein , Carnegie Mellon University, Pittsburgh, PA
Tiberiu Chelcea , Carnegie Mellon University, Pittsburgh, PA
Tobias Bjerregaard , TU Denmark, Lyngby, Denmark
Girish Venkataramani , Carnegie Mellon University, Pittsburgh, PA
pp. 231-236

Memory access optimizations in instruction-set simulators (PDF)

Prabhat Mishra , University of Florida, Gainesville, FL
Mehrdad Reshadi , University of California Irvine, Irvine, CA
pp. 237-242

Enabling unrestricted automated synthesis of portable hardware accelerators for virtual machines (Abstract)

Laura Pozzi , Ecole Polytechnique Federale de Lausanne (EPFL), Lausanne, Switzerland
Paolo Ienne , Ecole Polytechnique Federale de Lausanne (EPFL), Lausanne, Switzerland
Christophe Dubach , Ecole Polytechnique Federale de Lausanne (EPFL), Lausanne, Switzerland
Miljan VuletiC , Ecole Polytechnique Federale de Lausanne (EPFL), Lausanne, Switzerland
pp. 243-248

Retargetable generation of TLM bus interfaces for MP-SoC platforms (PDF)

Heinrich Meyr , RWTH Aachen University, Germany
Rainer Leupers , RWTH Aachen University, Germany
Achim Nohl , CoWare, Inc., CA
Gerd Ascheid , RWTH Aachen University, Germany
Tim Kogel , CoWare, Inc., CA
Tom Michiels , CoWare, Inc., CA
Andreas Wieferink , RWTH Aachen University, Germany
pp. 249-254

Automatic network generation for system-on-chip communication design (PDF)

Andreas Gerstlauer , University of California, Irvine, CA
Daniel D. Gajski , University of California, Irvine, CA
Rainer Domer , University of California, Irvine, CA
Dongwan Shin , University of California, Irvine, CA
pp. 255-260

Service dependency graph: an efficient model for hardware/software interfaces modeling and generation for SoC design (PDF)

Ahmed Amine Jerraya , TIMA Laboratory, CEDEX, France
Frederic Rousseau , TIMA Laboratory, CEDEX, France
Aimen Bouchhima , TIMA Laboratory, CEDEX, France
Mohamed-wassim Youssef , TIMA Laboratory, CEDEX, France
Arnaud Grasset , TIMA Laboratory, CEDEX, France
Wander Cesario , TIMA Laboratory, CEDEX, France
Lobna Kriaa , TIMA Laboratory, CEDEX, France
Adriano Sarmento , TIMA Laboratory, CEDEX, France
pp. 261-266

A multicast inter-task communication protocol for embedded multiprocessor systems (PDF)

Wido Kruijtzer , Philips Research Laboratories, The Netherlands
Gustavo Marrero , University of Las Palmas, Las Palmas GC, Spain
Antonio Nunez , University of Las Palmas, Las Palmas GC, Spain
Tomas Bautista , University of Las Palmas, Las Palmas GC, Spain
Victor Reyes , University of Las Palmas, Las Palmas GC, Spain
pp. 267-272

An automated exploration framework for FPGA-based soft multiprocessor systems (PDF)

Kurt Keutzer , University of California at Berkeley, CA
Kaushik Ravindran , University of California at Berkeley, CA
Nadathur Satish , University of California at Berkeley, CA
Yujia Jin , University of California at Berkeley, CA
pp. 273-278

FlexPath NP: a network processor concept with application-driven flexible processing paths (PDF)

Andreas Herkersdorf , Munich University of Technology, Munich, Germany
Thomas Wild , Munich University of Technology, Munich, Germany
Rainer Ohlendorf , Munich University of Technology, Munich, Germany
pp. 279-284

Hardware/software partitioning of software binaries: a case study of H.264 decode (PDF)

Gordon McGregor , Freescale Semiconductor
Brian Einloth , Freescale Semiconductor
Frank Vahid , University of California, Riverside
Greg Stitt , University of California, Riverside
pp. 285-290

Designing real-time H.264 decoders with dataflow architectures (PDF)

Suleyman Sair , NC State University
Youngsoo Kim , NC State University
pp. 291-296

Novel architecture for loop acceleration: a case study (PDF)

Sri Parameswaran , University of New South Wales, Sydney, Australia
Newton Cheung , University of New South Wales, Sydney, Australia
Seng Lin Shee , University of New South Wales, Sydney, Australia
pp. 297-302

Improving superword level parallelism support in modern compilers (Abstract)

Manuel Prieto , Universidad Complutense, Madrid, Spain
Luis Pinuel , Universidad Complutense, Madrid, Spain
F. Catthoor , Interuniversity MicroElectronic Center (IMEC), Leuven, Belgium
Francisco Tirado , Universidad Complutense, Madrid, Spain
Christian Tenllado , Universidad Complutense, Madrid, Spain
pp. 303-308

Iterational retiming: maximize iteration-level parallelism for nested loops (PDF)

Zili Shao , University of Texas at Dallas
Edwin H.-m. Sha , University of Texas at Dallas
Meilin Liu , University of Texas at Dallas
Chun Xue , University of Texas at Dallas
pp. 309-314

Rappit: framework for synthesis of host-assisted scripting engines for adaptive embedded systems (PDF)

Pai H. Chou , University of California, Irvine, CA
Qiang Xie , University of California, Irvine, CA
Jiwon Hahn , University of California, Irvine, CA
pp. 315-320

Dynamic phase analysis for cycle-close trace generation (PDF)

Rajesh Gupta , University of California, San Diego, CA
Brad Calder , University of California, San Diego, CA
Jeremy Lau , University of California, San Diego, CA
Cristiano Pereira , University of California, San Diego, CA
pp. 321-326

Grand challenges in embedded systems (PDF)

John Glossner , Sandbridge Technologies
Trevor Mudge , University of Michigan, Ann Arbor, MI
Wayne Wolf , Princeton University, Princeton, NJ
Chris Rowen , Tensilica
Feng Zhao , Microsoft Research
Janos Sztipanovits , Vanderbilt University
pp. 333

Comparing the size of .NET applications with native code (PDF)

Erven Rohou , STMicroelectronics, Manno, Switzerland
Roberto Costa , STMicroelectronics, Manno, Switzerland
pp. 99-104
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