CSDL - International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS

Hardware/software codesign and system synthesis, International conference on (2004)

Stockholm, Sweden

Sept. 8, 2004 to Sept. 10, 2004

ISBN: 1-58113-937-3

TABLE OF CONTENTS

International Conference on Hardware/Software Codesign and Systems Synthesis (IEEE Cat. No.04TH8785) (PDF)

pp. 0_1

International Conference on Hardware/Software Codesign and System Synthesis (PDF)

pp. i

Message from the chairs - Welcome to CODES+ISSS 2004! (PDF)

pp. iii

CODES+ISSS'04 Organizing Committee (PDF)

pp. ix-x

2003-2004 Steering Committee (PDF)

pp. xii

Future challenges in embedded systems (PDF)

A. Cuomo , Adv. Syst. Technol., STMicroelectronics, USA

pp. 1

Organic computing - on the feasibility of controlled emergence (PDF)

C. Muller-Schloer , Inst. of Syst. Eng. - Syst. & Comput. Archit. (SRA), Hannover Univ., Germany

pp. 2-5

A loop accelerator for low power embedded VLIW processors (PDF)

B. Mathew , Sch. of Comput., Utah Univ., Salt Lake City, UT, USA

A. Davis , Sch. of Comput., Utah Univ., Salt Lake City, UT, USA

pp. 6-11

Dual-pipeline heterogeneous ASIP design (PDF)

S. Radhakrishnan , Sch. of Comput. Sci. & Eng., New South Wales Univ., Sydney, NSW, Australia

Hui Guo , Sch. of Comput. Sci. & Eng., New South Wales Univ., Sydney, NSW, Australia

S. Parameswaran , Sch. of Comput. Sci. & Eng., New South Wales Univ., Sydney, NSW, Australia

pp. 12-17

Fast cycle-accurate simulation and instruction set generation for constraint-based descriptions of programmable architectures (PDF)

S.J. Weber , Electron. Res. Lab., California Univ., Berkeley, CA, USA

M.W. Moskewicz , Electron. Res. Lab., California Univ., Berkeley, CA, USA

M. Gries , Electron. Res. Lab., California Univ., Berkeley, CA, USA

C. Sauer

K. Keutzer

pp. 18-23

Introduction

CODES+ISSS?04 Organizing Committee (PDF)

pp. ix-x

CODES+ISSS?04 Technical Program Committee (PDF)

pp. xi

CODES+ISSS?04 Steering Committee (PDF)

pp. xii

Additional Reviewers (PDF)

pp. xiii-xiv

Keynote

Future Challenges in Embedded Systems (PDF)

Andrea Cuomo , STMicroelectronics

pp. 1

Session A1: Special Session on Organic Computing

Organic Computing — On the Feasibility of Controlled Emergence (Abstract)

C. M?ller-Schloer , Universit?t Hannover

pp. 2-5

Session B1: New Design Techniques for Application Specific Processors

A Loop Accelerator for Low Power Embedded VLIW Processors (Abstract)

Binu Mathew , University of Utah

Al Davis , University of Utah

pp. 6-11

Dual-Pipeline Heterogeneous ASIP Design (Abstract)

Swarnalatha Radhakrishnan , University of New South Wales

Hui Guo , University of New South Wales

Sri Parameswaran , University of New South Wales

pp. 12-17

Fast Cycle-Accurate Simulation and Instruction Set Generation for Constraint-Based Descriptions of Programmable Architectures (Abstract)

Scott J. Weber , University of California at Berkeley

Matthew W. Moskewicz , University of California at Berkeley

Matthias Gries , University of California at Berkeley

Christian Sauer , Infineon Technologies

Kurt Keutzer , University of California at Berkeley

pp. 18-23

Session A2: Advances in Software and Hardware Synthesis Techniques for DSP Applications

Hardware Synthesis from Coarse-Grained Dataflow Specification for Fast HW/SW Cosynthesis (Abstract)

Hyunuk Jung , Seoul National University

Soonhoi Ha , Seoul National University

pp. 24-29

Efficient Mapping of Hierarchical Trees on Coarse-Grain Reconfigurable Architectures (Abstract)

F. Rivera , Universidad Complutense

M. Sanchez-Elez , Universidad Complutense

M. Fernandez , Universidad Complutense

R. Hermida , Universidad Complutense

N. Bagherzadeh , University of California at Irvine

pp. 30-35

Detecting Overflow Detection (Abstract)

Vladimir Kotlyar , Sandbridge Technologies, Inc.

Mayan Moudgill , Sandbridge Technologies, Inc.

pp. 36-41

Memory Accesses Management During High Level Synthesis (Abstract)

Gwenolé Corre , University of South Brittany

Eric Senn , University of South Brittany

Pierre Bomel , University of South Brittany

Nathalie Julien , University of South Brittany

Eric Martin , University of South Brittany

pp. 42-47

Session B2: Multiprocessor SoC: Design Strategies and Programming Models

Parallel Programming Models for a Multi-Processor SoC Platform Applied to High-Speed Traffic Management (Abstract)

Pierre G. Paulin , STMicroelectronics

Chuck Pilkington , STMicroelectronics

Michel Langevin , STMicroelectronics

Essaid Bensoudane , STMicroelectronics

Gabriela Nicolescu , Ecole Polytechnique de Montreal

pp. 48-53

Benchmark-Based Design Strategies for Single Chip Heterogeneous Multiprocessors (Abstract)

JoAnn M. Paul , Carnegie Mellon University

Donald E. Thomas , Carnegie Mellon University

Alex Bobrek , Carnegie Mellon University

pp. 54-59

Automatic Synthesis of System on Chip Multiprocessor Architectures for Process Networks (Abstract)

Basant Kumar Dwivedi , Indian Institute of Technology Delhi

Anshul Kumar , Indian Institute of Technology Delhi

M. Balakrishnan , Indian Institute of Technology Delhi

pp. 60-65

Modeling Operation and Microarchitecture Concurrency for Communication Architectures with Application to Retargetable Simulation (Abstract)

Xinping Zhu , Princeton University

Wei Qin , Princeton University

Sharad Malik , Princeton University

pp. 66-71

Panel 1

Secure and Safety-Critical vs. Insecure, Non Safety-Critical Embedded Systems: Do They Require Completely Different Design Approaches? (PDF)

Peter Marwedel , University of Dortmund and ICD

Catherine Gebotys , University of Waterloo

pp. 72-73

Keynote

Cellular Handset Technology System Requirements and Integration Trends (PDF)

Sven Mattisson , Ericsson Mobile Platforms AB

pp. 74

Session A3: New Modeling Approaches and Their Application

Transaction Level Modeling: Flows and Use Models (Abstract)

Adam Donlin , Xilinx Research Labs

pp. 75-80

Exploiting Polymorphism in HW Design: a Case Study in the ATM Domain (Abstract)

Luigi Pomante , CEFRIEL

pp. 81-85

Facilitating Reuse in Hardware Models with Enhanced Type Inference (Abstract)

Manish Vachharajani , Princeton University

Neil Vachharajani , Princeton University

Sharad Malik , Princeton University

David I. August , Princeton University

pp. 86-91

System-on-Chip Validation Using UML and CWL (Abstract)

Qiang Zhu , Fujitsu Laboratories LTD.

Ryosuke Oishi , Fujitsu Laboratories LTD.

Takashi Hasegawa , Fujitsu Limited

Tsuneo Nakata , Fujitsu Laboratories LTD.

pp. 92-97

Session B3: Energy-Aware Compiling and Scheduling

Compiler-Directed Code Restructuring for Reducing Data TLB Energy (Abstract)

M. Kandemir , Pennsylvania State University

I. Kadayif , Canakkale Onsekiz Mart University

G. Chen , Pennsylvania State University

pp. 98-103

Dynamic Overlay of Scratchpad Memory for Energy Minimization (Abstract)

Manish Verma , University of Dortmund

Lars Wehmeyer , University of Dortmund

Peter Marwedel , University of Dortmund

pp. 104-109

CPU Scheduling for Statistically-Assured Real-Time Performance and Improved Energy Efficiency (PDF)

Haisang Wu , Virginia Tech

Binoy Ravindran , Virginia Tech

E. Douglas Jensen , The MITRE Corporation

Peng Li , Virginia Tech

pp. 110-115

Session A4: System-Level Design Space Exploration for Hardware-Software Partitioning and Platform Instantiation

Power-Performance Trade-Offs for Reconfigurable Computing (Abstract)

Juanjo Noguera , Hewlett-Packard

Rosa M. Badia , Hewlett-Packard

pp. 116-121

Efficient Search Space Exploration for HW-SW Partitioning (Abstract)

Sudarshan Banerjee , University of California at Irvine

Nikil Dutt , University of California at Irvine

pp. 122-127

Tuning SoC Platforms for Multimedia Processing: Identifying Limits and Tradeoffs (Abstract)

Alexander Maxiaguine , ETH Z?urich

Yongxin Zhu , National University of Singapore

Samarjit Chakraborty , National University of Singapore

Weng-Fai Wong , National University of Singapore

pp. 128-133

Session B4: Estimation and Design Techniques for Energy-Efficient Memory Systems

Energy-Efficient Flash-Memory Storage Systems with an Interrupt-Emulation Mechanism (Abstract)

Chin-Hsien Wu , National Taiwan University

Tei-Wei Kuo , National Taiwan University

Chia-Lin Yang , National Taiwan University

pp. 134-139

Memory System Design Space Exploration for Low-Power, Real-Time Speech Recognition (Abstract)

Rajeev Krishna , University of Michigan

Scott Mahlke , University of Michigan

Todd Austin , University of Michigan

pp. 140-145

Analytical Models for Leakage Power Estimation of Memory Array Structures (Abstract)

Mahesh Mamidipaka , University of California at Irvine

Kamal Khouri , Freescale/Motorola Inc.

Nikil Dutt , University of California at Irvine

Magdy Abadir , Freescale/Motorola Inc.

pp. 146-151

Session A5: Advances in Hardware/Software Co-Simulation Techniques

A Timing-Accurate HW/SW Co-Simulation of an ISS with SystemC (Abstract)

Luca Formaggio , Università di Verona

Franco Fummi , Università di Verona

Graziano Pravadelli , Università di Verona

pp. 152-157

RTOS-Centric Hardware/Software Cosimulator for Embedded System Design (Abstract)

Shinya Honda , Toyohashi University of Technology

Takayuki Wakabayashi , Toyohashi University of Technology

Hiroyuki Tomiyama , Nagoya University

Hiroaki Takada , Nagoya University

pp. 158-163

Fast Co-Simulation of Transformative Systems with OS Support (Abstract)

Zhengting He , University of Texas-Austin

Aloysius Mok , University of Texas-Austin

pp. 164-169

Session B5: NoC Design and Optimisation

Power-Aware Communication Optimization for Networks-on-Chips with Voltage Scalable Links (Abstract)

Dongkun Shin , Seoul National University

Jihong Kim , Seoul National University

pp. 170-175

Reducing Power and Latency in 2-D Mesh NoCs Using Globally Pseudochronous Locally Synchronous Clocking (Abstract)

Erland Nilsson , Royal Institute of Technology

Johnny Öberg , Royal Institute of Technology

pp. 176-181

Multi-Objective Mapping for Mesh-Based NoC Architectures (Abstract)

Giuseppe Ascia , University of Catania

Vincenzo Catania , University of Catania

Maurizio Palesi , University of Catania

pp. 182-187

Session A6: Software and Hardware Techniques for Performance Optimisation of Embedded Applications

Optimizing the Memory Bandwidth with Loop Fusion (Abstract)

Paul Marchal , IMEC/KULEUVEN

Jos? Ignacio G?mez , DACYA U.C.M.

Francky Catthoor , IMEC/KULEUVEN

pp. 188-193

Operation Tables for Scheduling in the Presence of Incomplete Bypassing (Abstract)

Aviral Shrivastava , University of California at Irvine

Eugene Earlie , Intel Labs

Nikil Dutt , University of California at Irvine

Alex Nicolau , Intel Labs

pp. 194-199

A Novel Deadlock Avoidance Algorithm and Its Hardware Implementation (Abstract)

Jaehwan Lee , Georgia Institute of Technology

Vincent John Mooney III , Georgia Institute of Technology

pp. 200-205

Session B6: Special Session

Design and Programming of Embedded Multiprocessors: An Interface-Centric Approach (Abstract)

Pieter van der Wolf , Philips Research

Erwin de Kock , Philips Research

Tomas Henriksson , Philips Research

Wido Kruijtzer , Philips Research

Gerben Essink , Philips Research

pp. 206-217

Session A7: New Techniques for Security and Reliability Enhancement in Embedded Systems

Current Flattening in Software and Hardware for Security Applications (Abstract)

Radu Muresan , University of Guelph

Catherine Gebotys , University of Waterloo

pp. 218-223

Low Energy Security Optimization in Embedded Cryptographic Systems (Abstract)

Catherine H. Gebotys , University of Waterloo

pp. 224-229

Analyzing Heap Error Behavior in Embedded JVM Environments (Abstract)

G. Chen , Pennsylvania State University

M. Kandemir , Pennsylvania State University

N. Vijaykrishnan , Pennsylvania State University

A. Sivasubramaniam , Pennsylvania State University

M. J. Irwin , Pennsylvania State University

pp. 230-235

Session B7: On-Chip Communication Architectures: Analysis and Optimisation

Power Analysis of System-Level On-Chip Communication Architectures (Abstract)

Kanishka Lahiri , NEC Laboratories America

Anand Raghunathan , NEC Laboratories America

pp. 236-241

Fast Exploration of Bus-Based On-Chip Communication Architectures (Abstract)

Sudeep Pasricha , University of California at Irvine

Nikil Dutt , University of California at Irvine

Mohamed Ben-Romdhane , Conexant Systems Inc.

pp. 242-247

Efficient Exploration of On-Chip Bus Architectures and Memory Allocation (Abstract)

Sungchan Kim , Seoul National University

Chaeseok Im , Seoul National University

Soonhoi Ha , Seoul National University

pp. 248-253

Panel 2

Embedded Systems Education: How to Teach the Required Skills? (PDF)

Peter Marwedel , University of Dortmund + ICD

Daniel Gajski , University of California at Irvine

Erwin De Kock , Philips

Hugo De Man , K.U. Leuven + IMEC

Peter Marwedel , University of Dortmund + ICD

Mariagiovanna Sami , Politechnico di Milano

Ingemar S?derquist , Saab

pp. 254-255

Author Index

Author Index (PDF)

pp. 256