CODES+ISSS?04 Organizing Committee (PDF)

CODES+ISSS?04 Technical Program Committee (PDF)

CODES+ISSS?04 Steering Committee (PDF)

Additional Reviewers (PDF)

Future Challenges in Embedded Systems (PDF)

Organic Computing — On the Feasibility of Controlled Emergence (Abstract)

A Loop Accelerator for Low Power Embedded VLIW Processors (Abstract)

Dual-Pipeline Heterogeneous ASIP Design (Abstract)

Fast Cycle-Accurate Simulation and Instruction Set Generation for Constraint-Based Descriptions of Programmable Architectures (Abstract)

Hardware Synthesis from Coarse-Grained Dataflow Specification for Fast HW/SW Cosynthesis (Abstract)

Efficient Mapping of Hierarchical Trees on Coarse-Grain Reconfigurable Architectures (Abstract)

Detecting Overflow Detection (Abstract)

Memory Accesses Management During High Level Synthesis (Abstract)

Parallel Programming Models for a Multi-Processor SoC Platform Applied to High-Speed Traffic Management (Abstract)

Benchmark-Based Design Strategies for Single Chip Heterogeneous Multiprocessors (Abstract)

Automatic Synthesis of System on Chip Multiprocessor Architectures for Process Networks (Abstract)

Modeling Operation and Microarchitecture Concurrency for Communication Architectures with Application to Retargetable Simulation (Abstract)

Secure and Safety-Critical vs. Insecure, Non Safety-Critical Embedded Systems: Do They Require Completely Different Design Approaches? (PDF)

Cellular Handset Technology System Requirements and Integration Trends (PDF)

Transaction Level Modeling: Flows and Use Models (Abstract)

Exploiting Polymorphism in HW Design: a Case Study in the ATM Domain (Abstract)

Facilitating Reuse in Hardware Models with Enhanced Type Inference (Abstract)

System-on-Chip Validation Using UML and CWL (Abstract)

Compiler-Directed Code Restructuring for Reducing Data TLB Energy (Abstract)

Dynamic Overlay of Scratchpad Memory for Energy Minimization (Abstract)

CPU Scheduling for Statistically-Assured Real-Time Performance and Improved Energy Efficiency (PDF)

Power-Performance Trade-Offs for Reconfigurable Computing (Abstract)

Efficient Search Space Exploration for HW-SW Partitioning (Abstract)

Tuning SoC Platforms for Multimedia Processing: Identifying Limits and Tradeoffs (Abstract)

Energy-Efficient Flash-Memory Storage Systems with an Interrupt-Emulation Mechanism (Abstract)

Memory System Design Space Exploration for Low-Power, Real-Time Speech Recognition (Abstract)

Analytical Models for Leakage Power Estimation of Memory Array Structures (Abstract)

A Timing-Accurate HW/SW Co-Simulation of an ISS with SystemC (Abstract)

RTOS-Centric Hardware/Software Cosimulator for Embedded System Design (Abstract)

Fast Co-Simulation of Transformative Systems with OS Support (Abstract)

Power-Aware Communication Optimization for Networks-on-Chips with Voltage Scalable Links (Abstract)

Reducing Power and Latency in 2-D Mesh NoCs Using Globally Pseudochronous Locally Synchronous Clocking (Abstract)

Multi-Objective Mapping for Mesh-Based NoC Architectures (Abstract)

Optimizing the Memory Bandwidth with Loop Fusion (Abstract)

Operation Tables for Scheduling in the Presence of Incomplete Bypassing (Abstract)

A Novel Deadlock Avoidance Algorithm and Its Hardware Implementation (Abstract)

Design and Programming of Embedded Multiprocessors: An Interface-Centric Approach (Abstract)

Current Flattening in Software and Hardware for Security Applications (Abstract)

Low Energy Security Optimization in Embedded Cryptographic Systems (Abstract)

Analyzing Heap Error Behavior in Embedded JVM Environments (Abstract)

Power Analysis of System-Level On-Chip Communication Architectures (Abstract)

Fast Exploration of Bus-Based On-Chip Communication Architectures (Abstract)

Efficient Exploration of On-Chip Bus Architectures and Memory Allocation (Abstract)

Embedded Systems Education: How to Teach the Required Skills? (PDF)

Author Index (PDF)