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Computer and Information Technology, International Conference on (2010)
Bradford, West Yorkshire, UK
June 29, 2010 to July 1, 2010
ISBN: 978-0-7695-4108-2
pp: 1257-1262
Data encryption process can easily be quite complicated and usually requires significant computation time and power despite significant simplifications. This paper discusses about pipelined and non-pipelined implementation of one of the most commonly used symmetric encryption algorithm, Data Encryption Standard (DES). The platform used for this matter is, Xilinx new high performance silicon foundation, Virtex-6 Field Programmable Gate Array technology. Finite state machine is used only in non-pipelined implementation, and it is not implemented for the pipelined approach. The testing of the implemented design shows that it is possible to generate data in 16 clock cycles when non-pipelined approach is employed. When pipelined approach is employed on the other hand, 17 clock signals are required for the initial phase only, and one clock signal is sufficient afterwards for each data generation cycle. The Very High Speed Integrated Circuit Hardware Description Language (VHDL) is used to program the design.
Data Encryption Standard, Field Programmable Gate Arrays, Very High Speed Integrated Circuit Hardware Description Language, Finite State Machine

O. Gemikonakli, E. Ever and S. Taherkhani, "Implementation of Non-Pipelined and Pipelined Data Encryption Standard (DES) Using Xilinx Virtex-6 FPGA Technology," 2010 IEEE 10th International Conference on Computer and Information Technology (CIT), Bradford, 2010, pp. 1257-1262.
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