Computer and Information Technology, International Conference on (2010)
Bradford, West Yorkshire, UK
June 29, 2010 to July 1, 2010
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/CIT.2010.59
Modern embedded processors highly rely on the accuracy of branch predictors. Large predictors with complex prediction algorithms cause more power consumption of the embedded systems which are already power hungry. Power consumed by a branch predictor can be reduced by removing unnecessary predictor accesses. In this paper we present the design of a low power branch predictor that exploits the well-behaved branches. Well-behaved branches are loops which show continuous Taken branch results. Our method is based on the Taken Branch Identification Table(TBIT). It maintains well-behaved taken-branch data that are updated by a 2-bit saturated counter learning algorithm. Through the TBIT, we eliminate unnecessary lookups and updates of a predictor when a well-behaved taken-branch instruction is executed repeatedly such as in a loop. The effectiveness of the proposed branch predictor is confirmed by the simulation results of the SPECint2000 and Mediabench benchmarks. The experimental results show that with negligible performance degradation, our method can reduce the power consumption of branch predictor about 40% and the processor total power consumption about 2.3% on average.
branch predictor, low power, embedded processor, bimodal predictor, power reduction
E. Jo, S. Kim and H. Kim, "Low Power Branch Predictor for Embedded Processors," 2010 IEEE 10th International Conference on Computer and Information Technology (CIT), Bradford, 2010, pp. 107-114.