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Computer and Information Technology, International Conference on (2010)
Bradford, West Yorkshire, UK
June 29, 2010 to July 1, 2010
ISBN: 978-0-7695-4108-2
pp: 54-61
Network on Chip (NoC) is considered as the promising diagram of interconnection mechanism for future chip multiprocessors. As the number of processing elements (PE) on chip keeps growing, the delay for simultaneous memory references of these PEs is emerging as a serious bottleneck on high performance. One major part of this delay is from the Memory Management Unit (MMU) due to its centralized structure. In this paper, we propose a novel distributed MMU architecture for NoC-based CMPs, which can effectively reduce the bottleneck effect in contrast of traditional MMU. We discuss the benefit of this architecture in aspects of TLB hit rate, network communication efficiency, memory bandwidth and coherence. Experimental results show that the distributed MMU structure significantly improves network throughput balance and lowers communicational delay.
memory management unit, network on chip, on-chip communication

C. Tianzhou, Y. Like, S. Qingsong, C. Man, X. Bin and Q. Fuming, "Distributed Memory Management Units Architecture for NoC-based CMPs," 2010 IEEE 10th International Conference on Computer and Information Technology (CIT), Bradford, 2010, pp. 54-61.
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