The Community for Technology Leaders
Computer and Information Technology, International Conference on (2010)
Bradford, West Yorkshire, UK
June 29, 2010 to July 1, 2010
ISBN: 978-0-7695-4108-2
pp: 33-40
We present a fine-grain parallel processor chip which can be embedded in very compact machine vision systems, e.g. in 3d stacked die assemblies. Smart and fast vision systems are frequently required in industrial environments to automatically detect and inspect objects, e.g. on an assembly line. The chip die has a size of 25 mm² and is manufactured using a 0.18 um CMOS technology. The chip processes binary images with a maximum resolution of 320x240 pixels (QVGA) supplied by a separate closely-linked image sensor array. It is possible to process an image in multiple cycles where a set of morphological operations can be subsequently combined depending on the image processing problem. In addition the chip is able to compute more complex user-defined programs, e.g. to skeletonize images. The output data can be a preprocessed image or projection representations in horizontal, vertical and diagonal direction, which reduces the data amount. Therefore a faster image post-processing is supported, e.g. to calculate object's momenta. The chip is driven by a 40 MHz clock. As result a base morphological operation including image in/output needs only 250 us. For even faster data in/output a ROI (region of interest) can be defined. Two standardized interfaces (JTAG, SPI) allow to parameterize as well as to program the circuit.
Embedded image processors, dynamically programmable ASIP

A. Loos, J. Gröbel, D. Fey and M. Schmidt, "Dynamically Programmable Image Processor for Compact Vision Systems," 2010 IEEE 10th International Conference on Computer and Information Technology (CIT), Bradford, 2010, pp. 33-40.
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