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Cluster Computing and the Grid, IEEE International Symposium on (2011)
Newport Beach, California USA
May 23, 2011 to May 26, 2011
ISBN: 978-0-7695-4395-6
pp: 53-62
ABSTRACT
The multicore revolution and the ever-increasing complexity of computing systems is dramatically changing sys-tem design, analysis and programming of computing platforms. Future architectures will feature hundreds to thousands of simple processors and on-chip memories connected through a network-on-chip. Architectural simulators will remain primary tools for design space exploration, software development and performance evaluation of these massively parallel architectures. However, architectural simulation performance is a serious concern, as virtual platforms and simulation technology are not able to tackle the complexity of thousands of core future scenarios. The main contribution of this paper is the development of a new simulation approach and technology for many core processors which exploit the enormous parallel processing capability of low-cost and widely available General Purpose Graphic Processing Units (GPGPU). The simulation of many-core architectures exhibits indeed a high level of parallelism and is inherently parallelizable, but GPGPU acceleration of architectural simulation requires an in-depth revision of the data structures and functional partitioning traditionally used in parallel simulation. We demonstrate our GPGPU simulator on a target architecture composed by several cores (i.e. ARM ISA based), with instruction and data caches, connected through a Network-on-Chip (NoC). Our experiments confirm the feasibility of our approach.
INDEX TERMS
CUDA, GPGPU, ISS, NoC, simulation, manycore
CITATION
Luca Benini, Christian Pinto, David Atienza, Andrea Marongiu, Shivani Raghav, Martino Ruggiero, "GPGPU-Accelerated Parallel and Fast Simulation of Thousand-Core Platforms", Cluster Computing and the Grid, IEEE International Symposium on, vol. 00, no. , pp. 53-62, 2011, doi:10.1109/CCGrid.2011.64
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