2016 Fourth International Symposium on Computing and Networking (2016)

Hiroshima, Japan

Nov. 22, 2016 to Nov. 25, 2016

ISSN: 2379-1896

ISBN: 978-1-5090-2655-5

pp: 436-442

ABSTRACT

The non-von Neumann computer architecture has been widely studied towards preparing for the post-Moore era. The authors implemented the architecture, which finds the lower energy state of the Ising model using circuit operations inspired by simulated annealing, in SRAM-based integrated circuits. Our previous prototype was suited for the Ising model because of its simple and typical structure such as its three-dimensional lattice topology, but it could not be applied to real world applications. A reconfigurable prototyping environment is needed to develop the architecture, and to make it suitable for applications. Here, we describe an FPGA-based prototyping environment to develop the architecture of the annealing processor for the Ising model. We implemented the new architecture using the prototyping environment. The new architecture performs approximated simulated annealing for the Ising model, and it supports a highly complex topology. It consists of units having fully-connected multiple spins. Multiple units are placed in a two-dimensional lattice topology, and the neighboring units are connected to perform interactions between spins. The number of logic elements is reduced by sharing the operator among multiple spins within the unit. Furthermore, the pseudo-random number generator, which produces the random pulse sequences for annealing, is also shared among all the units. As a result, the number of logic elements is reduced to less than 1/10, and the solution accuracy becomes comparable to the simulated annealing running on a conventional computer.

INDEX TERMS

Computer architecture, Topology, Integrated circuit modeling, Computational modeling, Simulated annealing, Prototypes

CITATION

C. Yoshimura, M. Hayashi, T. Okuyama and M. Yamaoka, "FPGA-based Annealing Processor for Ising Model,"

*2016 Fourth International Symposium on Computing and Networking(CANDAR)*, Hiroshima, Japan, 2016, pp. 436-442.

doi:10.1109/CANDAR.2016.0081

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