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2016 Fourth International Symposium on Computing and Networking (2016)
Hiroshima, Japan
Nov. 22, 2016 to Nov. 25, 2016
ISSN: 2379-1896
ISBN: 978-1-5090-2655-5
pp: 415-421
Deep neural networks are widely used for many applications such as image classification, speech recognition and natural language processing because of their high recognition rate. Since general-purpose processors such as CPUs and GPUs are not energy efficient for such neural networks, application specific hardware accelerators for neural networks (a.k.a. neural network accelerators or NNAs) have been proposed to improve the energy efficiency. There are many studies to increase the energy efficiency of NNAs, but few studies focus on task allocation on the accelerators. This paper provides the first exploration of task mapping to cores within NNAs for the increased performance. Intuitively, a well-tuned task mapping has less amount of communication between cores. To confirm this assumption, we tested two types of task mappings that generate different amount of communication between cores on an NNA. Our experimental results show that the number of communication between cores strongly affects the execution cycle of the NNA and the most effective task mapping differs depending on the size of neural networks.
Multicore processing, Artificial neural networks, Biological neural networks, Neurons, Buffer storage, Program processors

S. Shindo, M. Ohba, T. Tsumura and S. Miwa, "Evaluation of Task Mapping on Multicore Neural Network Accelerators," 2016 Fourth International Symposium on Computing and Networking(CANDAR), Hiroshima, Japan, 2016, pp. 415-421.
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