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2016 Fourth International Symposium on Computing and Networking (2016)
Hiroshima, Japan
Nov. 22, 2016 to Nov. 25, 2016
ISSN: 2379-1896
ISBN: 978-1-5090-2655-5
pp: 77-83
ABSTRACT
Lock-based thread synchronization techniques have been commonly used in parallel programming on multi-core processors. However, lock can cause deadlocks and poor scalabilites, and Transactional Memory (TM) has been proposed and studied for lock-free synchronization. On TMs, transactions are executed speculatively in parallel as long as they do not encounter any conflicts on shared variables. On general HTMs, hardware implementations of TM, conflicts can degrade the performance of HTM because of the overhead for re-execution of transactions. To address this problem, various transaction scheduling algorithms for avoiding conflicts have been proposed. However in the existing algorithms, execution path variation is not considered at all. Some transactions have branch instructions, and they cause execution path variations of transaction, resulting in poor efficacy of the scheduling algorithms. In this paper, we propose a novel concurrency control based on the execution time of transactions with considering execution path variation. The result of the experiment shows that the execution time of HTM is reduced 61.6% at a maximum, and 13.8% on average with 16 threads.
INDEX TERMS
History, Message systems, System recovery, Instruction sets, Hardware, Scheduling algorithms
CITATION

A. Hirota, K. Mashita and T. Tsumura, "A Concurrency Control in Hardware Transactional Memory Considering Execution Path Variation," 2016 Fourth International Symposium on Computing and Networking(CANDAR), Hiroshima, Japan, 2016, pp. 77-83.
doi:10.1109/CANDAR.2016.0026
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