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2014 Second International Symposium on Computing and Networking (CANDAR) (2014)
Shizuoka, Japan
Dec. 10, 2014 to Dec. 12, 2014
ISBN: 978-1-4799-4152-0
pp: 614-616
ABSTRACT
This work focuses on measuring the number of GPU clock cycles necessary to execute load/store instructions in both bank conflict and bank conflict-free shared memory access patterns. To this end, a varying number of parameters have been considered in the experiments, including the number of warps (w), the number of memory bank conflicts (k) as well as the number of load/store instructions (l) per warp. From the analysis of the experimental results, it was possible to obtain an estimate (E) on the number of the clock cycles necessary to execute l load/store instructions. The estimate is given by E = w · l · k · c1 + c2, where c1 and c2 are constants assuming values 1.047 and 337.7, respectively. From the above results, we believe that obtained estimated can be used as an approximation on the number of clock cycles necessary to execute load and store instructions.
INDEX TERMS
Clocks, Graphics processing units, Instruction sets, Synchronization, Message systems, Assembly, Memory management
CITATION

S. Okamoto, Y. Ito, K. Nakano and J. L. Bordim, "Thorough Evaluation of GPU Shared Memory Load and Store Instructions," 2014 Second International Symposium on Computing and Networking (CANDAR), Shizuoka, Japan, 2014, pp. 614-616.
doi:10.1109/CANDAR.2014.42
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