2014 Second International Symposium on Computing and Networking (CANDAR) (2014)
Dec. 10, 2014 to Dec. 12, 2014
This paper presents a runtime resource management scheme named Cache Balancer that improves the utilization of on-chip shared caches and reduces access latencies in chip multiprocessor systems. Cache Balancer incorporates an access rate based memory allocator that improves utilization of on-chip cache resources resulting in up to 60% lower contention at cache banks. Furthermore, it uses information regarding the memory access characteristics of application tasks in order to obtain an optimal task mapping at runtime, and consequently achieves up to 22% lower execution times as compared to existing proposals.
Resource management, Pain, Runtime, Sensitivity, System-on-chip, Round robin
J. d. Klerk, S. S. Kumar and R. v. Leuken, "Cache Balancer: Access Rate and Pain Based Resource Management for Chip Multiprocessors," 2014 Second International Symposium on Computing and Networking (CANDAR), Shizuoka, Japan, 2014, pp. 453-456.