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Computer Architectures for Machine Perception, International Workshop on (1997)
Como, ITALY
Oct. 20, 1997 to Oct. 22, 1997
ISBN: 0-8186-7987-5
TABLE OF CONTENTS

Foreword (PDF)

pp. viii
Session 1: Architecture I

Processor/Memory/Array Size Tradeoffs in the Design of SIMD Arrays for a Spatially Mapped Workload (Abstract)

Renoy Sam , University of Houston
Owais Kidwai , University of Houston
Anisha Anand , University of Houston
Charles C. Weems , University of Massachusetts
Martin C. Herbordt , University of Houston
pp. 12

A 10 GIPS SIMD Processor for PC-based Real-Time Vision Applications --- Architecture, Algorithm Implementation and Language Support (Abstract)

Yoshihiro Fujita , Incubation Center, NEC Corporation
Sholin Kyo , Incubation Center, NEC Corporation
Nobuyuki Yamashita , Incubation Center, NEC Corporation
Shin'ichiro Okazaki , Incubation Center, NEC Corporation
pp. 22

The CC/IPP, an MIMD-SIMD architecture for image processing and pattern recognition (Abstract)

J. Vogelbruch , Pattern Recognition Group, Delft Univ. of Technol., Netherlands
P. Jonker , Pattern Recognition Group, Delft Univ. of Technol., Netherlands
pp. 33
Session 2: Languages and Environments I

DAISY: A Distributed Architecture for Intelligent System (Abstract)

A. Chella , Universita' di Palermo
B. Lenzitti , Universita' di Palermo
S. Gaglio , Universita' di Palermo
P. Storniolo , Universita' di Palermo
D. Intravaia , Universita' di Palermo
A. Messina , Universita' di Palermo
G. Gerardi , Universita' di Palermo
I. Infantino , Universita' di Palermo
R. Pirrone , Universita' di Palermo
G. Lo Bosco , Universita' di Palermo
V. Di Gesu' , Universita' di Palermo
pp. 42

A specific compilation scheme for image processing architecture (Abstract)

H. Essafi , IRISA, Rennes, France
F. Bodin , IRISA, Rennes, France
M. Pic , IRISA, Rennes, France
pp. 56

External Loop Unrolling of Image Processing Programs: Optimal Register Allocation for RISC architectures (Abstract)

N. Zingirian , Universita' degli Studi di Padova
M. Maresca , Universita' degli Studi di Padova
pp. 61
Session 3: Intelligent Sensors

Analog sensor processing using exposure control. A new concept for high speed image processing (Abstract)

A. Astrom , Dept. of Electr. Eng., Linkoping Univ., Sweden
E. Astrand , Dept. of Electr. Eng., Linkoping Univ., Sweden
pp. 68

Motion Vision Sensor Architecture with Asynchronous Self-Signaling Pixels (Abstract)

Denis Poussart , Laval University
Miguel Arias-Estrada , Laval University
Marc Tremblay , HexaVision Technologies Inc.
pp. 75

Hardware-Software Aspects of Shift-Register Based NEWS Networks for the Focal Plane (Abstract)

A. Jullian , CTME/GIP, F94114 Arcueil, France
T.M. Bernard , CTME/GIP, F94114 Arcueil, France
D. Mercier , CTME/GIP, F94114 Arcueil, France
R. Nguyen , CTME/GIP, F94114 Arcueil, France
pp. 84
Session 4: VLSI I

A Dedicated Image Processor Exploiting both Spatial and Instruction-Level Parallelism (Abstract)

Leonardo M. Reyneri , Politecnico di Torino
Roberto Passerone , Politecnico di Torino
Alberto Broggi , Universita` di Parma
Francesco Gregoretti , Politecnico di Torino
Massimo Bertozzi , Universita` di Parma
Gianni Conte , Universita` di Parma
Claudio Sansoe , Politecnico di Torino
pp. 106

Investigating real-time validation of real-time image processing ASICs (Abstract)

I.C. Kraljic , Ecole Polytech., Montreal, Que., Canada
F.S. Verdier , Ecole Polytech., Montreal, Que., Canada
G.M. Quenot , Ecole Polytech., Montreal, Que., Canada
B. Zavidovique , Ecole Polytech., Montreal, Que., Canada
pp. 116
Session 5: Configurable Computing

FPGA-based Computing in Computer Vision (Abstract)

Anil K. Jain , Michigan State University
Nalini K. Ratha , Thomas J. Watson Research Center
pp. 128

Multilayer Perceptrons on Splash 2 (Abstract)

Nalini K. Ratha , Thomas J. Watson Research Center
Anil K. Jain , Michigan State University
pp. 138

Parallel Object Recognition on an FPGA-based Configurable Computing Platform (Abstract)

Viktor K. Prasanna , University of Southern California, Los Angeles
Seonil Choi , University of Southern California, Los Angeles
Yongwha Chung , Electronics and Telecommunications Research Institute
pp. 143

Real-time Hierarchical Visual Tracking Using a Configurable Computing Machine (PDF)

Peter M. Athanas , The Bradley Department of Electrical and Computer Engineering Virginia Tech
A. Lynn Abbott , The Bradley Department of Electrical and Computer Engineering Virginia Tech
Bharadwaj Pudipeddi , The Bradley Department of Electrical and Computer Engineering Virginia Tech
pp. 153
Session 6: Languages and Environments II

Making a Dataparallel Language Portable for Massively Parallel Array Computers (Abstract)

James H. Burrill , University of Massachusetts
Martin C. Herbordt , University of Houston
Charles C. Weems , University of Massachusetts
pp. 160

An Interactive Tool for C.V. Tutorials (Abstract)

M. Pini , DIS - Universita` di Pavia
D. Codega , DIS - Universita` di Pavia
A. Biancardi , DIS - Universita` di Pavia
V. Cantoni , DIS - Universita` di Pavia
pp. 170

Context: A New Paradigm to Control Distributed Perceptual Systems (Abstract)

Vito Di Gesu , Universita' di Palermo
Francesco Isgro , Heriot-Watt University, UK
pp. 175

A Parallelizing Method for Implementing Image Processing Tasks on SIMD Linear Processor Arrays (Abstract)

Yoshihiro Fujita , Incubation Center, NEC Corporation
Nobuyuki Yamashita , Incubation Center, NEC Corporation
Sholin Kyo , Incubation Center, NEC Corporation
Shin'ichiro Okazaki , Incubation Center, NEC Corporation
pp. 180
Session 7: Algorithms

Hough transform implementation on a reconfigurable highly parallel architecture (Abstract)

M. Mahmoud , Integrated Inf. & Energy Syst. Lab., NTT Human Interface Labs., Kanagawa, Japan
T. Ogura , Integrated Inf. & Energy Syst. Lab., NTT Human Interface Labs., Kanagawa, Japan
M. Nakanishi , Integrated Inf. & Energy Syst. Lab., NTT Human Interface Labs., Kanagawa, Japan
pp. 186

Page segmentation using a pyramidal architecture (Abstract)

L. Cinque , Dipartimento di Inf. e Sistemistica, Pavia Univ., Italy
L. Lombardi , Dipartimento di Inf. e Sistemistica, Pavia Univ., Italy
G. Manzini , Dipartimento di Inf. e Sistemistica, Pavia Univ., Italy
V. Cantoni , Dipartimento di Inf. e Sistemistica, Pavia Univ., Italy
pp. 195

A Fast Parallel Algorithm for Stereovision (Abstract)

Rolf D. Henkel , University of Bremen
pp. 200
Session 8: Novel Approaches

Circuital Markov random fields for analog edge detection (Abstract)

M. Parodi , Dept. of Biophys. & Electron. Eng., Genoa Univ., Italy
C. Regazzoni , Dept. of Biophys. & Electron. Eng., Genoa Univ., Italy
M. Storace , Dept. of Biophys. & Electron. Eng., Genoa Univ., Italy
pp. 220

Image Processing in a Tree of Peano Coded Images (Abstract)

Guna Seetharaman , Univ. SW Louisiana
Bertrand Zavidovique , Universite Paris XI
pp. 229

Asynchronous SIMD: an architectural concept for high performance image processing (Abstract)

C. Weems , Comput. Sci. Dept., Massachusetts Univ., Amherst, MA, USA
pp. 235
Session 9: Architecture II

A general purpose SliM-II image processor (Abstract)

Soohwan Ong , Sch. of Electr. & Electron. Eng., Ajou Univ., Suwon, South Korea
Taihoon Cho , Sch. of Electr. & Electron. Eng., Ajou Univ., Suwon, South Korea
Myung H. Sunwoo , Sch. of Electr. & Electron. Eng., Ajou Univ., Suwon, South Korea
Changhee Lee , Sch. of Electr. & Electron. Eng., Ajou Univ., Suwon, South Korea
Hyunman Chang , Sch. of Electr. & Electron. Eng., Ajou Univ., Suwon, South Korea
pp. 253

The DARPA image understanding motion benchmark (Abstract)

C. Weems , Comput. Sci. Dept., Massachusetts Univ., Amherst, MA, USA
S. Dropsho , Comput. Sci. Dept., Massachusetts Univ., Amherst, MA, USA
G. Weaver , Comput. Sci. Dept., Massachusetts Univ., Amherst, MA, USA
J. Burrill , Comput. Sci. Dept., Massachusetts Univ., Amherst, MA, USA
R. Kumar , Comput. Sci. Dept., Massachusetts Univ., Amherst, MA, USA
pp. 260

A Scalable Architecture for Low and Intermediate Level Image Processing (Abstract)

J.G.E. Olk , Delft University of Technology
P.P. Jonker , Delft University of Technology
pp. 270
Session 10: VLSI II

A New Real Time Edge Linking Algorithm and its VLSI Implementation (Abstract)

Amjad Hajjar , Colorado State University
Tom Chen , Colorado State University
pp. 280

A Cost-Effective Morphological Filter Architecture (Abstract)

Soohwan Ong , Ajou University
Myung H. Sunwoo , Ajou University
pp. 285

A VLSI architecture for computing the optimal correspondence of string subsequences (Abstract)

N. Ranganathan , Center for Microelectron. Res., Univ. of South Florida, Tampa, FL, USA
R. Motamarri , Center for Microelectron. Res., Univ. of South Florida, Tampa, FL, USA
pp. 290

Towards a VHDL-based Synthesis of a Wavelet Transform Processor (Abstract)

D. Rizzo , University of Pavia
M. Ferretti , University of Pavia
pp. 295

Author Index (PDF)

pp. 300
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