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The time-dependent variation caused by Negative Bias Temperature Instability (NBTI) is agreed to be one of the main reliability concerns in integrated circuits implemented with current nanotechnology nodes. NBTI increases the threshold voltage of pMOS transistors: hence, it slows down signal propagation along logic paths between flip-flops. It may cause intermittent faults and, ultimately, permanent functional failures in processor circuits. In this paper, we study an NBTI mitigation approach in processor designs by rejuvenation of pMOS transistors along NBTI-critical paths. The method incorporates hierarchical fast, yet accurate modelling of NBTI-induced delays at transistor, gate and path levels for generation of rejuvenation Assembler programs using an Evolutionary Algorithm. These programs are applied further as an execution overhead to drive those pMOS transistors to the recovery phase, which are the most critical for the NBTI-induced path delay in processors. The experimental results demonstrate efficiency of evolutionary generation and significant reduction of NBTI-induced delays by the rejuvenation stimuli with an execution overhead of 0.1% or less. The proposed approach aims at extending the reliable lifetime of nanoelectronic processors.
Negative bias temperature instability, Thermal variables control, Aging, Computational modeling, Stress, Voltage control, Frequency control

F. Pellerey et al., "Rejuvenation of NBTI-Impacted Processors Using Evolutionary Generation of Assembler Programs," 2016 IEEE 25th Asian Test Symposium(ATS), Hiroshima, Japan, 2016, pp. 304-309.
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