The Community for Technology Leaders
2016 IEEE 25th Asian Test Symposium (2016)
Hiroshima, Japan
Nov. 21, 2016 to Nov. 24, 2016
ISSN: 2377-5386
ISBN: 978-1-5090-3809-1
pp: 150-155
ABSTRACT
Deviations in the first-order parameters of CMOS cells can lead to severe errors in the functional and time domain. With increasing sensitivity of these parameters to manufacturing defects and variation, parametric and parasitic-aware fault simulation is becoming crucial in order to support test pattern generation. Traditional approaches based on gate-level models are not sufficient to represent and capture the impact of deviations in these parameters in either an efficient or accurate manner. Evaluation at electrical level, on the other hand, severely lacks execution speed and quickly becomes inapplicable to larger designs due to high computational demands.This work presents a novel fault simulation approach considering first-order parameters in CMOS circuits to explicitly capture CMOS-specific behavior in the functional and time domain with transistor granularity. The approach utilizes massive parallelization in order to achieve high-throughput acceleration on Graphics Processing Units (GPUs) by exploiting parallelism of cells, stimuli and faults. Despite the more precise level of abstraction, the simulator is able to process designs with millions of gates and even outperforms conventional simulation at logic level in terms of modeling accuracy and simulation speed.
INDEX TERMS
Circuit faults, Integrated circuit modeling, Semiconductor device modeling, Transistors, Logic gates, Computational modeling, Timing
CITATION

E. Schneider and H. Wunderlich, "High-Throughput Transistor-Level Fault Simulation on GPUs," 2016 IEEE 25th Asian Test Symposium(ATS), Hiroshima, Japan, 2016, pp. 150-155.
doi:10.1109/ATS.2016.9
96 ms
(Ver 3.3 (11022016))