2016 IEEE 25th Asian Test Symposium (2016)
Nov. 21, 2016 to Nov. 24, 2016
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ATS.2016.49
IR-drop induced false capture failures and test clock stretch are severe problems in at-speed scan testing. We propose a new method to efficiently and accurately identify these problems. For the first time, our approach considers the additional dynamic power caused by glitches, the spatial and temporal distribution of all toggles, and their impact on both logic paths and the clock tree without time-consuming electrical simulations.
Delays, Clocks, Logic gates, Switches, Estimation, Switching circuits
S. Holst et al., "Timing-Accurate Estimation of IR-Drop Impact on Logic- and Clock-Paths During At-Speed Scan Test," 2016 IEEE 25th Asian Test Symposium(ATS), Hiroshima, Japan, 2016, pp. 19-24.