2015 IEEE 24th Asian Test Symposium (ATS) (2015)
Nov. 22, 2015 to Nov. 25, 2015
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ATS.2015.26
Small gate delay faults (SDFs) are not detectable at-speed, if they can only be propagated along short paths. These hidden delay faults (HDFs) do not influence the circuit's behavior initially, but they may indicate design marginalities leading to early-life failures, and therefore they cannot be neglected. HDFs can be detected by faster-than-at-speed test (FAST), where typically several different frequencies are used to maximize the coverage. A given set of test patterns P potentially detects a HDF if it contains a test pattern sensitizing a path through the fault site, and the efficiency of FAST can be measured as the ratio of actually detected HDFs to potentially detected HDFs. The paper at hand targets maximum test efficiency with a minimum number of frequencies. The procedure starts with a test set for transition delay faults and a set of preselected equidistant frequencies. Timing-accurate simulation of this initial setup identifies the hard-to-detect faults, which are then targeted by a more complex timing-aware ATPG procedure. For the yet undetected HDFs, a minimum number of frequencies are determined using an efficient hypergraph algorithm. Experimental results show that with this approach, the number of test frequencies required for maximum test efficiency can be reduced considerably. Furthermore, test set inflation is limited as timing-aware ATPG is only used for a small subset of HDFs.
Circuit faults, Delays, Logic gates, Time-frequency analysis, Automatic test pattern generation, Clocks
M. Kampmann, M. A. Kochte, E. Schneider, T. Indlekofer, S. Hellebrand and H. Wunderlich, "Optimized Selection of Frequencies for Faster-Than-at-Speed Test," 2015 IEEE 24th Asian Test Symposium (ATS), Mumbai, India, 2015, pp. 109-114.