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2015 IEEE 24th Asian Test Symposium (ATS) (2015)
Mumbai, India
Nov. 22, 2015 to Nov. 25, 2015
ISSN: 2377-5386
ISBN: 978-1-4673-9739-1
pp: 103-108
ABSTRACT
IR-drop induced by launch switching activity (LSA) in capture mode during at-speed scan testing increases delay along not only logic paths (LPs) but also clock paths (Cps). Excessive extra delay along LPs compromises test yields due to false capture failures, while excessive extra delay along CPs compromises test quality due to test clock stretch. This paper is the first to mitigate the impact of LSA on both LPs and CPs with a novel LCPA (Logic/Clock Path-Aware) at-speed scan test generation scheme, featuring (1) a new metric for assessing the risk of false capture failures based on the amount of LSA around both LPs and CPs, (2) a procedure for avoiding false capture failures by reducing LSA around LPs or masking uncertain test responses, and (3) a procedure for reducing test clock stretch by reducing LSA around CPs. Experimental results demonstrate the effectiveness of the LCPA scheme in improving test yields and test quality.
INDEX TERMS
Clocks, Delays, Testing, Circuit faults, Logic gates, Switches
CITATION

K. Asada et al., "Logic/Clock-Path-Aware At-Speed Scan Test Generation for Avoiding False Capture Failures and Reducing Clock Stretch," 2015 IEEE 24th Asian Test Symposium (ATS), Mumbai, India, 2015, pp. 103-108.
doi:10.1109/ATS.2015.25
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