2012 IEEE 21st Asian Test Symposium (2012)
Niigata, Japan Japan
Nov. 19, 2012 to Nov. 22, 2012
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ATS.2012.14
An iterative flow to generate test sets providing high fault coverage under extreme parameter variations is presented. The generation is guided by the novel metric of circuit coverage, calculated by massively parallel statistical fault simulation on GPGPUs. Experiments show that the statistical fault coverage of the generated test sets exceeds by far that achieved by standard approaches.
Circuit faults, Delay, Logic gates, Integrated circuit modeling, Automatic test pattern generation, Robustness, GPGPU, process variations, fault grading, Monte-Carlo, fault simulation, SAT-based, ATPG
A. Czutro et al., "Variation-Aware Fault Grading," 2012 IEEE 21st Asian Test Symposium(ATS), Niigata, Japan Japan, 2012, pp. 344-349.