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2012 IEEE 21st Asian Test Symposium (2012)
Niigata, Japan Japan
Nov. 19, 2012 to Nov. 22, 2012
ISSN: 1081-7735
ISBN: 978-1-4673-4555-2
pp: 338-343
ABSTRACT
This paper presents a high-level automatic test instruction generation (HATIG) technical that allows, for the first time, to test the scheduling unit of an out-of-order super scalar processor. This technique leverages on existing bounded model checking tools in order to generate software-based self-testing programs from a global EFSM model of the processor under test. The experimental results have demonstrated the efficiency of the proposed technique.
INDEX TERMS
Processor scheduling, Circuit faults, Out of order, Automatic test pattern generation, Registers, Out-of-Order Superscalar Processor, Automatic Test Instruction Generation, Bounded Model Chekcing, Software-Based Self-Testing
CITATION

Y. Zhang, A. Rezine, P. Eles and Z. Peng, "Automatic Test Program Generation for Out-of-Order Superscalar Processors," 2012 IEEE 21st Asian Test Symposium(ATS), Niigata, Japan Japan, 2012, pp. 338-343.
doi:10.1109/ATS.2012.43
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