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2012 IEEE 21st Asian Test Symposium (2012)
Niigata, Japan Japan
Nov. 19, 2012 to Nov. 22, 2012
ISSN: 1081-7735
ISBN: 978-1-4673-4555-2
pp: 326-331
When designing a system on chip (SoC), a test access mechanism (TAM) is required to deliver test data and to collect test responses from cores under test (CUTs). To facilitate the network on chip (NoC) testing, test engineers frequently focus on reusing the NoC as TAM, in which, communication infrastructure of the NoC (routers, interconnection links, protocolsc) is reused as TAM. While NoC reuse as TAM can achieve a low area overhead, test scheduling is a difficult issue, due to the fact that test data are exchanged in packets. Based on this drawback, this paper presents a new method which consists of reconfiguring the NoC hardware dynamically to act as a TAM. This configurability allows us to have the granularity of the traditional TAM which facilitates test scheduling, and the advantages of the NoC communication infrastructure, which give us the possibility of parallel testing, low area overhead and usage of the functional NoC frequencies. The proposed TAM is then compared to a conventional NoC reuse as TAM method and a TAM architecture named T2-TAM using two ITC'02 benchmark circuits. The presented results show a test time reduction between 6% and 55% while imposing less than 9.6% area overhead.
Wires, Routing, Testing, System-on-a-chip, Scheduling algorithms, Nickel, Dynamically reconfigurable NoC TAM, NoC, Test Access Mechanism, NoC reuse as TAM, NoC reconfigure as TAM

T. Sbiai and K. Namba, "NoC Dynamically Reconfigurable as TAM," 2012 IEEE 21st Asian Test Symposium(ATS), Niigata, Japan Japan, 2012, pp. 326-331.
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