2012 IEEE 21st Asian Test Symposium (2012)
Niigata, Japan Japan
Nov. 19, 2012 to Nov. 22, 2012
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ATS.2012.54
Process variation comes from several aspects during IC manufacturing, resulting in tremendous yield loss in advanced CMOS process. Recently, post-silicon tuning techniques that could adaptively manipulate failed chips to compensate the variations have been widely studied. Yet, full-chip adjustments can also increase dynamic and leakage power consumption. A fine-grain voltage-control architecture was proposed to tune only necessary parts of circuits. The corresponding diagnosis and tuning algorithm, however, require variable test clock strobing to measure path delays, which incurs a large test cost. In this paper, we propose to build a test data library that only uses a few fixed test clocks. We can then use the library to categorize the test results and sort the chips into different correction voltage tuning configurations. The experimental results show that with much lower cost (4% in average), the method can fix from 86%to 118% chip samples as compared to a satisfiability (SAT)-based method that requires accurate path delay measurement.
Clocks, Delay, Tuning, Support vector machines, Training data, Systematics, Accuracy
J. Kuo, T. Hsu and J. Liou, "Test Cost Reduction for Performance Yield Recovery by Classification of Multiple-Clock Test Data," 2012 IEEE 21st Asian Test Symposium(ATS), Niigata, Japan Japan, 2012, pp. 320-325.