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2012 IEEE 21st Asian Test Symposium (2012)
Niigata, Japan Japan
Nov. 19, 2012 to Nov. 22, 2012
ISSN: 1081-7735
ISBN: 978-1-4673-4555-2
pp: 296-301
ABSTRACT
Testing asynchronous circuits has been a challenge for several years. Especially, the nondeterministic timing behavior leads to problems during test, since the occurrence of test responses is not aligned to tester cycles. For this reason a test processor solution for asynchronous circuits has been recently provided, compensating the timing uncertainty. This is achieved by realizing an elastic test via asynchronous handshaking. Based on this approach we present a method for generating functional test patterns for the provided architecture.
INDEX TERMS
Protocols, Registers, Asynchronous circuits, Synchronization, Arrays, timing nondeterminism, test processor, functional test, pattern generation, asynchronous circuits, handshake protocols
CITATION

S. Zeidler, C. Wolf, M. Krstic and R. Kraemer, "Functional Pattern Generation for Asynchronous Designs in a Test Processor Environment," 2012 IEEE 21st Asian Test Symposium(ATS), Niigata, Japan Japan, 2012, pp. 296-301.
doi:10.1109/ATS.2012.40
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