2012 IEEE 21st Asian Test Symposium (2012)
Niigata, Japan Japan
Nov. 19, 2012 to Nov. 22, 2012
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ATS.2012.21
In this paper, we present, for the 1-bit/stage pipelined ADC, a self-characterization technique that quantifies the per-stage capacitor ratio and comparator offset - the two main nonlinearity sources. In the proposed loop test, two adjacent pipelined stages are reconfigured to form a loop. Then, DC test stimuli are applied. The capacitor ratio and comparator offset of the stage under test are derived from the recorded output sequences. Numerical simulations are performed to validate the proposed technique.
Calibration, Capacitors, Testing, Estimation error, Clocks, Numerical simulation, pipelined ADC, mixed-signal, design-for-test
Y. Chou, J. Huang and X. Huang, "A Built-In Characterization Technique for 1-Bit/Stage Pipelined ADC," 2012 IEEE 21st Asian Test Symposium(ATS), Niigata, Japan Japan, 2012, pp. 284-289.