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2012 IEEE 21st Asian Test Symposium (2012)
Niigata, Japan Japan
Nov. 19, 2012 to Nov. 22, 2012
ISSN: 1081-7735
ISBN: 978-1-4673-4555-2
pp: 272-277
ABSTRACT
High test power in logic BIST is a serious problem not only for production test, but also for board test, system debug or field test. Many low power BIST approaches that focus on scan-shift power or capture power have been proposed. However, it is known that a half of scan-shift power is compensated by test responses, which is difficult to control in those approaches. This paper proposes a novel approach that directly reduces scan-out power by modifying some flip-flops' values in scan chains at the last capture. Experimental results show that the proposed method reduces scan-out power up to 30% with little loss of test coverage.
INDEX TERMS
Filling, Circuit faults, Logic gates, Built-in self-test, Vectors, Switches, Delay, shift power, low power, BIST, multi-cycle test
CITATION

S. Wang, Y. Sato, K. Miyase and S. Kajihara, "A Scan-Out Power Reduction Method for Multi-cycle BIST," 2012 IEEE 21st Asian Test Symposium(ATS), Niigata, Japan Japan, 2012, pp. 272-277.
doi:10.1109/ATS.2012.50
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