2012 IEEE 21st Asian Test Symposium (2012)
Niigata, Japan Japan
Nov. 19, 2012 to Nov. 22, 2012
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ATS.2012.73
Software-based diagnosis of scan test failures has been an established method for localizing defects as part of the failure analysis process for digital semiconductor devices. Diagnosis software determines the defect type and location for each failing device based on the design description, scan test patterns, and tester fail data. This gives failure analysis engineers or engineers involved in non-destructive testing and evaluation, a proven, and highly effective way of defect localization and identification, complementing their traditional, hardware-based failure analysis machine approach. Recent disruptions in yield enhancement capabilities such as dramatic increase in design sensitive defects and longer failure analysis cycle times have necessitated the development of new technology. As a result, better diagnosis, better failure data collection and better statistics method have been developed to analyze volume diagnosis data to provide value in a range of applications including technology yield ramp and product yield improvement. This tutorial describes how diagnosis-driven yield analysis (DDYA) accelerates time to root cause of yield loss and identifies yield limiters from volume diagnosis data. The underlying technology key to the methodology is an extremely accurate and consequential single-die diagnosis of scan test failures. Furthermore, specialized statistical analysis is used to identify and separate systematic yield limiters in seemingly random fail data and select the most suitable devices for failure analysis. The presentation will cover fundamentals as well as recent advances in diagnosis technology and diagnosis results analysis that drive the adoption of this approach:1) Layout-aware diagnosis provides detailed defect classifications that are significantly more valuable for yield analysis than defect locations alone.2) Scan chain diagnosis identifies and localizing defects in the test structures, scan chains themselves, simplifying a process that can otherwise be tedious and performed using dedicated and costly equipment.3) Novel machine learning techniques separate the noise that exists in diagnosis data to determine the underlying root causes represented in a population of failing devices from test data alone. This dramatically reduces the number of costly physical failure analysis to identify systematic defects. DFM analysis has significant impact to yield. A new approach will be explored to correlate DFM analysis and diagnosis results to identify DFM rules that most succinctly describe the design-process induced systematic defects.
Failure analysis, Object recognition, Systematics, Tutorials, Life estimation, Graphics, Manufacturing, Failure Analysis, Diagnosis, Yield
W. Cheng and F. Kuo, "Embedded Tutorial Summary: Diagnosis for Accelerating Yield and Failure Analysis," 2012 IEEE 21st Asian Test Symposium(ATS), Niigata, Japan Japan, 2012, pp. 271.