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2012 IEEE 21st Asian Test Symposium (2012)
Niigata, Japan Japan
Nov. 19, 2012 to Nov. 22, 2012
ISSN: 1081-7735
ISBN: 978-1-4673-4555-2
pp: 258-263
This paper reviews the theory and introduces the architecture for a clock source with low phase noise and for measuring timing jitter. This approach utilizes a sample mean and sum of two random variables, and can be implemented in CMOS or SiGe BiCMOS circuits.
Clocks, Phase noise, Timing jitter, Voltage-controlled oscillators, Phase locked loops, Phase frequency detector, bias error, histogram, cumulative distribution function, probability density function, random variable, fail counter, random error

K. Niitsu, T. J. Yamaguchi, M. Ishida and H. Kobayashi, "Post-Silicon Jitter Measurements," 2012 IEEE 21st Asian Test Symposium(ATS), Niigata, Japan Japan, 2012, pp. 258-263.
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