2012 IEEE 21st Asian Test Symposium (2012)
Niigata, Japan Japan
Nov. 19, 2012 to Nov. 22, 2012
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ATS.2012.22
This paper, as a case study and tutorial, discusses testing methods for general PLL features and their operating margin. These methods can be applied all for analog-, digital- and PW-PLLs. There are various kinds of on-chip measurement macros which can be applied for the PLL testing, and for the direction toward digitally assisted analog circuit testing, it is shown that a digitally controlled variable delay and a time to digital converter have a big possibility for PLL testing using only digital signals.
Phase locked loops, Delay, Phase frequency detector, Jitter, Clocks, Testing, System-on-a-chip
T. Nakura, T. Iizuka and K. Asada, "Impact of All-Digital PLL on SoC Testing," 2012 IEEE 21st Asian Test Symposium(ATS), Niigata, Japan Japan, 2012, pp. 252-257.