The Community for Technology Leaders
2012 IEEE 21st Asian Test Symposium (2012)
Niigata, Japan Japan
Nov. 19, 2012 to Nov. 22, 2012
ISSN: 1081-7735
ISBN: 978-1-4673-4555-2
pp: 245
ABSTRACT
Summary form only given, as follows. Dynamic faults are more likely to occur in more scaled technologies. One of the challenges in testing Static Random Access Memory (SRAM) is 'dynamic faults,' which are sensitized by multiple read or write operations. These faults cannot be sensitized by a single read or write operation. Paper 7B.1 [Renesas] discusses SRAM dynamic stability testing. This includes read-write disturbance issues and an advanced on-chip test circuit which provides a word-line pulse of variable pulse widths to the internal nodes of the dual-port SRAM under measurement. Post-silicon data validated that the proposed circuit can screen the read-write disturb failures. Technology scaling enables us to trade off amplitude resolution for time resolution. This is called Staszewski's law. Accordingly, both internal and external tests are also shifting from voltage centric tests to timing centric tests. Post-silicon jitter/phase noise characterization of the first-silicon fabricated for a PLL design can provide both actual timing uncertainty information and BER performance degradation due to jitter. Paper 7B.2 [Univ. of Tokyo] addresses all-digital test circuits and on-chip jitter analyzer macros to characterize advanced all-digital PLLs. Moreover, in order to measure sub-ps timing jitter, implementation of a practical on-chip circuit faces severe difficulties associated with providing a jitter-free reference clock to the on-chip instrument and realizing a fail counter of high time resolution. Paper 7B.3 [Gunma Univ.] introduces a new architecture for measuring on-chip timing jitter. The new architecture requires no reference clock and can directly measure timing jitter by combining a fail counter of appropriate time resolution and a time difference amplifier with a gain of 100. Finally, an ATE based solution is required in order to perform high-volume post-silicon validation of high-speed serial I/O (HSIO) devices and test fabricated silicon copies. Paper 7B.4 [Advantest] demonstrates that an active test fixture approach can test 28 Gb/s HSIO devices by MUX / DEMUX of currently available 7 Gb/s pin electronics channels. BER jitter bathtub curves were also successfully measured with a time resolution of 400 fs.
INDEX TERMS
CITATION

T. J. Yamaguchi, "Session Summary IV: Post-Silicon Measurements and Tests: Analog Test and High-Speed I/O Test II," 2012 IEEE 21st Asian Test Symposium(ATS), Niigata, Japan Japan, 2012, pp. 245.
doi:10.1109/ATS.2012.87
86 ms
(Ver 3.3 (11022016))