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2012 IEEE 21st Asian Test Symposium (2012)
Niigata, Japan Japan
Nov. 19, 2012 to Nov. 22, 2012
ISSN: 1081-7735
ISBN: 978-1-4673-4555-2
pp: 239-244
ABSTRACT
Scan based at-speed testing has become mandatory in industry to detect delay defects today in order to maintain test quality and reduce test cost. However, the effects of power supply droop during test application often introduce timing uncertainty, such as clock stretch and additional gate delay. It leads to false failure and test escape during test and makes the application of the at-speed scan testing become a challenge task to screen out delay defects successfully. In this paper, we review existing studies about the power supply droop and the methods to reduce its impact on at-speed scan testing.
INDEX TERMS
Clocks, Power supplies, Logic gates, Switches, Delay, Testing, RLC circuits, test power reduction, Power supply droop, structural test, at-speed scan test
CITATION

X. Lin, "Power Supply Droop and Its Impacts on Structural At-Speed Testing," 2012 IEEE 21st Asian Test Symposium(ATS), Niigata, Japan Japan, 2012, pp. 239-244.
doi:10.1109/ATS.2012.63
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