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2012 IEEE 21st Asian Test Symposium (2012)
Niigata, Japan Japan
Nov. 19, 2012 to Nov. 22, 2012
ISSN: 1081-7735
ISBN: 978-1-4673-4555-2
pp: 233-238
ABSTRACT
An overview of test generation approaches to maximize power supply noise is provided and issues related to and research directions for generation of test vectors with representative power are discussed. In particular, to facilitate the early design and validation of the power delivery network (PDN), the need for automatic high-level test generation to create functionally representative vectors that cause worst-case power events, which stress the power grid, is described.
INDEX TERMS
Vectors, Switches, Automatic test pattern generation, Logic gates, Power grids, Delay, Analytical models, ATPG, :power analysis, power grid, test generation
CITATION

P. Varma, "Current and Future Directions in Automatic Test Pattern Generation for Power Delivery Network Validation," 2012 IEEE 21st Asian Test Symposium(ATS), Niigata, Japan Japan, 2012, pp. 233-238.
doi:10.1109/ATS.2012.68
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