2012 IEEE 21st Asian Test Symposium (2012)
Niigata, Japan Japan
Nov. 19, 2012 to Nov. 22, 2012
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ATS.2012.60
We present a fast power analysis flow called Power MAX in this paper. Power MAX is specially devised for power evaluation of test vectors. It has the capability of power calculation and peak current identification for each test cycle. This cycle-by-cycle power and current monitoring ensures the power-safety of test vectors before they are loaded to testers. Power MAX is layout-aware, thus able to pinpoint hotspots as well. The entire power analysis flow is seamlessly integrated into test vector simulation. Power MAX fills the gap of test power analysis flows that achieves both efficiency and accuracy. We believe our flow is the first attempt to address vector-based power evaluation problem especially for test mode. Results on industrial hard macros show that Power MAX provides high power-integrity sign-off accuracy with low CPU runtime.
Switches, Monitoring, Layout, Vectors, Logic gates, Capacitance, Analytical models, test power and power grid analysis, power bumps, power analysis, weighted switching activity
W. Zhao and M. Tehranipoor, "PowerMAX: Fast Power Analysis during Test," 2012 IEEE 21st Asian Test Symposium(ATS), Niigata, Japan Japan, 2012, pp. 227-232.