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2012 IEEE 21st Asian Test Symposium (2012)
Niigata, Japan Japan
Nov. 19, 2012 to Nov. 22, 2012
ISSN: 1081-7735
ISBN: 978-1-4673-4555-2
pp: 221-226
ABSTRACT
Managing the power consumption of circuits and systems is challenging not only during functional operations but also during manufacturing test. In this paper, we first explain why it is important to control power consumption during test application. We will introduce the basic concepts and discuss issues arising from excessive power dissipation during test. Then, we explain how it is possible to control power consumption during test. We will provide an overview of existing structural and algorithmic solutions for power-aware testing, and we will show how low power circuits can be tested safely without affecting yield and reliability.
INDEX TERMS
Clocks, Power demand, Logic gates, Power dissipation, Automatic test pattern generation, Switches
CITATION

A. Bosio, L. Dilillo, P. Girard, A. Todri and A. Virazel, "Why and How Controlling Power Consumption during Test: A Survey," 2012 IEEE 21st Asian Test Symposium(ATS), Niigata, Japan Japan, 2012, pp. 221-226.
doi:10.1109/ATS.2012.30
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