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2012 IEEE 21st Asian Test Symposium (2012)
Niigata, Japan Japan
Nov. 19, 2012 to Nov. 22, 2012
ISSN: 1081-7735
ISBN: 978-1-4673-4555-2
pp: 143-148
This paper presents a method for automatic diagnosis and correction of design bugs in processors. Given a golden sequential instruction-set architecture model of a processor and its erroneous detailed cycle-accurate model at micro-architecture level, we employ a symbolic simulator and a property checker in an iterative process to formally find the candidate buggy locations and their corresponding fixes, without requiring an error model. We have shown the effectiveness of our method on a complex out-of-order super scalar processors supporting atomic execution.
Multiplexing, Program processors, Radiation detectors, Computer bugs, Registers, Error correction, Logic gates, processors, design error diagnosis, design error correction, micro architecture debugging, formal verification

A. M. Gharehbaghi and M. Fujita, "Error Model Free Automatic Design Error Correction of Complex Processors Using Formal Methods," 2012 IEEE 21st Asian Test Symposium(ATS), Niigata, Japan Japan, 2012, pp. 143-148.
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