2012 IEEE 21st Asian Test Symposium (2012)
Niigata, Japan Japan
Nov. 19, 2012 to Nov. 22, 2012
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ATS.2012.31
Conventional edge triggered flip-flops sample a data signal synchronizing with single clock edge. If a noise signal occurs around the clock edge, flip-flops result in malfunction. Then, we have proposed dual edge triggered flip-flops to solve this problem. The flip-flop has highly ability to prevent sampling a noise signal on a data line because it samples the data signal synchronizing with both of the rising edge and the falling edge. In this paper, we design a new circuit of the dual edge triggered flip-flops to improve circuit size, power consumption, and operation speed. In addition, we apply the dual edge triggered flip-flops to signal delay detection.
Delay, Noise, Clocks, Image edge detection, Synchronization, Flip-flops, signal delay, edge triggered flip-flops, clock edge, data line, noise, synchronous circuits
Y. Ohkawa and Y. Miura, "Dual Edge Triggered Flip-Flops for Noise Blocking and Application to Signal Delay Detection," 2012 IEEE 21st Asian Test Symposium(ATS), Niigata, Japan Japan, 2012, pp. 119-124.