2012 IEEE 21st Asian Test Symposium (2012)
Niigata, Japan Japan
Nov. 19, 2012 to Nov. 22, 2012
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ATS.2012.29
Shift and capture power management has become indispensable for modern complex low-power designs. Excessive shift power increases test application time and may jeopardize the shift operation correctness, excessive capture power during at-speed scan testing may lead to yield loss. This paper proposes a scan cell design which isolates scan cells output transitions in both shift and capture modes. Experimental results on larger ISCAS'89, ITC'99, and IWLS'05 benchmark circuits show that the proposed scan cell design lowers capture power consumptions with reasonable CPU times and test set inflation.
Tides, Automatic test pattern generation, IP networks, Computer architecture, Microprocessors, Circuit faults, Logic gates
Y. Lin, J. Huang and X. Wen, "A Transition Isolation Scan Cell Design for Low Shift and Capture Power," 2012 IEEE 21st Asian Test Symposium(ATS), Niigata, Japan Japan, 2012, pp. 107-112.