2012 IEEE 21st Asian Test Symposium (2012)
Niigata, Japan Japan
Nov. 19, 2012 to Nov. 22, 2012
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ATS.2012.26
In this work, we propose a novel scan architecture for 3-D ICs by considering the interconnection overhead of through-silicon-vias (TSVs). Since hotspots in 3-DICs often cause performance and reliability issues, we also developed a new test ordering scheme to avoid applying test vectors that could worsen the temperature distribution. Experimental results show that the peak temperature can be lowered by 20% by the 3-D scan tree architecture. When combined with the test ordering scheme, the 3-D scan tree can further reduce peak temperature by over 30%.
Vectors, Vegetation, Thermal analysis, Testing, Equations, Power demand, Heating
D. Xiang, K. Shen and Y. Deng, "A Thermal-Driven Test Application Scheme for 3-Dimensional ICs," 2012 IEEE 21st Asian Test Symposium(ATS), Niigata, Japan Japan, 2012, pp. 101-106.