The Community for Technology Leaders
2012 IEEE 21st Asian Test Symposium (2012)
Niigata, Japan Japan
Nov. 19, 2012 to Nov. 22, 2012
ISSN: 1081-7735
ISBN: 978-1-4673-4555-2
pp: 89-94
ABSTRACT
Shrinking feature size and higher integration on semiconductor device manufacturing technology bring a problem of the gap between the defect level estimated at the design stage from the reported one for fabricated devices. In this study, as one possible strategy to accurately estimate the defect level, we discuss on fault coverage estimation with more accuracy for the given test pattern set. We consider the probability that intermediate voltage caused by bridge/open defects is translated into logic values 0/1 at any of successive nodes. For each possible pair of signal lines in a given layout data, we execute critical area analysis. On the basis of critical areas obtained, we calculate weighted probabilistic bridge fault coverage, considering frequency of occurrence of each fault.
INDEX TERMS
Circuit faults, Bridge circuits, Probabilistic logic, Estimation, Layout, Manufacturing, Threshold voltage, critical area, weighted fault coverage, weighted probabilistic fault coverage, layout-aware
CITATION

M. Arai, Y. Shimizu and K. Iwasaki, "Note on Layout-Aware Weighted Probabilistic Bridge Fault Coverage," 2012 IEEE 21st Asian Test Symposium(ATS), Niigata, Japan Japan, 2012, pp. 89-94.
doi:10.1109/ATS.2012.53
95 ms
(Ver 3.3 (11022016))