2012 IEEE 21st Asian Test Symposium (2012)
Niigata, Japan Japan
Nov. 19, 2012 to Nov. 22, 2012
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ATS.2012.41
Test data compression has become a dominant approach to reduce the test cost today. Majority of test compression schemes are based on the fact that the generated test cubes have very few specified bits. This paper studies additional test cube properties and utilizes them to reduce the test data volume (TDV) further. Two approaches are proposed in this paper. The first one requires no additional hardware and the second one is based on the new DFT hardware, named background chains. The proposed approaches can be combined with other test compression schemes to achieve additional TDV reduction. The experimental results based on embedded deterministic test (EDT) show the proposed approaches achieve significant TDV reduction for industrial designs.
Vectors, Hardware, Encoding, Test data compression, Loading, Radiation detectors, Circuit faults, Scan Chains, Test Data Volume, Test Compression, ATPG, Test Cubes
X. Lin and J. Rajski, "On Utilizing Test Cube Properties to Reduce Test Data Volume Further," 2012 IEEE 21st Asian Test Symposium(ATS), Niigata, Japan Japan, 2012, pp. 83-88.