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2012 IEEE 21st Asian Test Symposium (2012)
Niigata, Japan Japan
Nov. 19, 2012 to Nov. 22, 2012
ISSN: 1081-7735
ISBN: 978-1-4673-4555-2
pp: 77-82
ABSTRACT
This paper presents a new multi-level EDT scheme to reduce scan channels of scan-based SoC designs. Multi-level EDT requires trivial modification on existing EDT scheme with two-pass encoding. Experimental results show that this scheme can reduce channel count by up to 30% without penalty of test coverage and pattern count.
INDEX TERMS
Equations, System-on-a-chip, Encoding, Ring generators, Phase shifters, Benchmark testing, Clocks, reduce scan channels, Embedded Deterministic Test (EDT), scan-based testing, test data compression, multi-level EDT
CITATION

G. Li, J. Qian, P. Li and G. Zuo, "Multi-level EDT to Reduce Scan Channels in SoC Designs," 2012 IEEE 21st Asian Test Symposium(ATS), Niigata, Japan Japan, 2012, pp. 77-82.
doi:10.1109/ATS.2012.70
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