2012 IEEE 21st Asian Test Symposium (2012)
Niigata, Japan Japan
Nov. 19, 2012 to Nov. 22, 2012
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ATS.2012.77
There are many attributes related to dependability: availability and reliability, confidentiality, integrity and maintainability. To design a "dependable" SOC could mean one or all of the following: fault tolerant design, redundancy design, "design for security" or simply to improve silicon validation in order to produce a more robust chip. In this paper, the author is going to examine three design techniques fall into the domain of design for dependability: silicon fault injection; harvestable design and design for security. There are many ways the system can be under "attack" and become faulty. Designing the system to be fault tolerant will increase the availability and reliability. One important element of a fault tolerant design is software ECO system for fault detection and correction. However, testing and validation of the fault detection and correction features require the creation of a faulty condition. In this paper, we will look at some IC design based fault injection techniques and their applications in software testing. Another technique to improve system availability and possibly improve system reliability is to add redundancy. Designs with redundant blocks are often called harvestable. Fault detection and isolation will be needed to separate between harvestable and faulty blocks. The detection and isolation processes are available during silicon detection or run time which will make increase system reliability. Harvestable designs are often a valid mean to improve device yield.User confidentiality and system integrity demand a "secured" IC design. Security features limit access to system data stored in IC in different security states. We will discuss the design for test challenges in the face of all the security features along with design's security mechanism.
Security, Fault tolerance, Fault tolerant systems, Availability, Silicon, Integrated circuits
J. Qian, "A Few Design Techniques for the "Dependability" of a SOC," 2012 IEEE 21st Asian Test Symposium(ATS), Niigata, Japan Japan, 2012, pp. 70.