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2012 IEEE 21st Asian Test Symposium (2012)
Niigata, Japan Japan
Nov. 19, 2012 to Nov. 22, 2012
ISSN: 1081-7735
ISBN: 978-1-4673-4555-2
pp: 68
ABSTRACT
As transistor geometry shrinks, the erroneous and spurious charge from a particle strike tends to be shared by multiple nodes and causes multiple nodes upset. Such SEU mechanism invalidates the hardening principle of protecting a single node in relatively larger technologies. SEU needs to be accordingly understood and evaluated. In an 28-nm design example, SEU can happen in 6-day interval if no mitigation technique is used.
INDEX TERMS
Random access memory, Single event upset, Reliability, Geometry, Transistors, Market research, Mesons, soft error, single-event upset (SEU), multiple cell upset (MCU)
CITATION

S. Baeg, J. Bae, S. Lee, C. S. Lim, S. H. Jeon and H. Nam, "Soft Error Issues with Scaling Technologies," 2012 IEEE 21st Asian Test Symposium(ATS), Niigata, Japan Japan, 2012, pp. 68.
doi:10.1109/ATS.2012.72
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